Differential interconnection circuits in programmable logic...

Details Differential interconnection circuits in programmable logic... Differential interconnection circuits in programmable logic...

2001-05-10

2003-02-04

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000, C326S041000, C326S086000, C326S090000, C326S056000, C327S108000

Reexamination Certificate

active

06515508

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic integrated circuit devices, and more particularly to the interconnection circuitry used in such devices. Examples of known programmable logic devices (“PLDs”) are shown in Cliff et al. U.S. Pat. Nos. 5,909,126 and 5,963,049.
PLDs typically include large numbers of regions of programmable logic and other resources such as memory, input/output circuits, etc., that are selectively interconnectable via programmable interconnection resources on the device. For example, each region of programmable logic on a PLD may be programmable to perform any of several relatively simple logic functions on several input signals applied to that region in order to produce one or more output signals indicative of the result of performing the selected logic function(s) on the input signals. The interconnection resources are programmable to convey signals to, from, and between the logic regions in any of a wide variety of patterns or configurations. For example, the interconnection resources may be used to concatenate several logic regions so that much more complex logic tasks can be performed than any one logic region can perform.
It is now typical to use a single conductor for each individual interconnection pathway or path segment in PLDs. Single NMOS pass gates (controlled by programmable memory elements or circuits on the PLD) are used for selectively interconnecting each conductor to other conductors to provide various signal routings through the interconnection resources of the device.
One trend in the design of PLDs is toward the use of lower power supply voltage and therefore lower internal signaling voltage. At lower power supply voltage the Vt drop of NMOS pass gates becomes a more significant fraction or percentage of the power supply voltage. This can lead to several problems in conventional PLD interconnection circuitry. For example, signaling slows down and the circuitry becomes increasingly susceptible to capacitive cross-talk between parallel conductors.
SUMMARY OF THE INVENTION
In accordance with the principles of this invention, differential signaling circuitry is used on a PLD. This differential signaling circuitry includes driver circuitry for converting a single input signal to a pair of differential signals. Two conductors are used to convey the differential signals from the driver circuitry. Receiver circuitry receives the two differential signals and converts them back to a single output signal. If switching or programmable routing is needed between the driver and the receiver, programmably controlled differential switching circuitry may be used to selectively connect two conductors to two other conductors. If a conductor pair may be driven by more than one driver, each driver may have programmably controlled connections to that conductor pair. Similarly, if a conductor pair may supply signals to more than one receiver, each receiver may have programmably controlled connections to that conductor pair. The adverse effects of capacitive coupling between a pair of differential signaling conductors and one or more other conductors that are adjacent and parallel to the differential signaling conductors may be reduced by effectively twisting the conductors in the differential signaling pair along the length of those conductors.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.


REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 5666354 (1997-09-01), Cecchi et al.
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5963049 (1999-10-01), Cliff et al.
patent: 5982192 (1999-11-01), Saito
patent: 6025742 (2000-02-01), Chan
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6353334 (2002-03-01), Schultz et al.
Xilinx, Multi-Drop LVDS with Virtex-E FPGAs, Sep. 1999, by Brunetti et al. pp. 1-11.

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