Differential input receiver with programmable failsafe

Details Differential input receiver with programmable failsafe Differential input receiver with programmable failsafe

2007-07-17

2007-07-17

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S030000

Reexamination Certificate

active

11071356

ABSTRACT:
In one embodiment, a circuit is provided that includes: a differential input receiver having a first input terminal and a second input terminal; a first programmable switch coupled to the first input terminal and coupled through a first resistor to a first voltage such that if the first programmable switch is closed, the first input terminal is pulled towards the first voltage; and a second programmable switch coupled to the second input terminal and coupled through a second resistor to a second voltage such that if the second programmable switch is closed, the second input terminal is pulled towards the second voltage, wherein the first and second programmable switches are programmed to be closed during a differential input mode of operation in which the differential input receiver processes differential input signals provided to the first and second input terminals.

REFERENCES:
patent: 5781028 (1998-07-01), Decuir
patent: 6188271 (2001-02-01), Wang et al.
patent: 6963219 (2005-11-01), Ghia et al.
National Semiconductor Corporation AN200184, Failsafe Biasing of LVDS Interfaces, Dec. 2001, pp. 1-4.
National Semiconductor, LVDS Owner's Manual, Low-Voltage Differential Signaling, 3rd Edition, Spring 2004, pp. 4-10-4-12, no month.
Fairchild Semiconductor, How to Apply SERDES Performance to Your Design, Edmond H. Suckow and Fairchild Semiconductor, 2003, pp. 1-18, no month.

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