Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Patent
1998-07-22
2000-09-05
Tokar, Michael
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
326 17, 326 34, 326 83, 326121, H03K 1716
Patent
active
061148725
ABSTRACT:
A differential input circuit includes a first differential circuit of a current mirror type for generating a first differential voltage by using an input voltage and a reference voltage, a second differential circuit of a current mirror type for generating a second differential voltage having a phase opposite to that of the first differential voltage by using the input voltage and the reference voltage, and a third differential circuit for generating an output voltage corresponding to a difference voltage of the first and second differential voltages by using the first and second differential voltages. A first clamping circuit for clamping the first differential voltage is provided between the first and third differential circuits. A second clamping circuit for clamping the second differential voltage is provided between the second and third differential circuits.
REFERENCES:
patent: 4608503 (1986-08-01), Wong et al.
patent: 4945262 (1990-07-01), Piasecki
patent: 5534789 (1996-07-01), Ting
patent: 5677642 (1997-10-01), Rehm et al.
patent: 5850158 (1998-12-01), Kattamann
Itoh, Super LSI Memory, Baifukan Co., Ltd., pp. 64-69, 1994.
Le Don Phu
Nippon Steel Corporation
Tokar Michael
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