Differential, high speed, ECL to CMOS converter

Details Differential, high speed, ECL to CMOS converter Differential, high speed, ECL to CMOS converter

1998-07-27

2001-06-26

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S066000, C326S084000

Reexamination Certificate

active

06252421

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This invention is related to the invention disclosed and claimed in co-pending U.S. patent application, filed of even date with the filing date of this application Ser. No. 09/123,208, the contents of which are hereby incorporated by reference in this Application.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the interfacing of high speed, low voltage, data streams with CMOS circuits and, more specifically, to converting low voltage, differential, ECL signal levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability.
2. Brief Description of the Prior Art
Differential Emitter Coupled Logic (ECL) circuitry is often used in high speed data transmission applications due to its small signal nature and resulting higher speed of operation. The differential aspect of these low level signals provides improved signal-to-noise, due to common mode operation at the receiving end of the transmission. However, it is important that these low level ECL signals be converted to higher levels without a significant degradation in speed and that the output of the converter has sufficient drive capability to make it useful for a particular application.
Existing circuits of this type often make the ECL to CMOS level conversion at the expense of speed and/or drive capability. Inherently, the lower ECL levels can be switched faster than the larger CMOS levels, but attempts to speed up the conversion process often diminish the output drive capability of the circuit. Representative prior circuits of this general type are shown in U.S. Pat. No. 5,726,588 to Fiedler, U.S. Pat. No. 55,606,268 to Van Brunt and U.S. Pat. No. 5,426,381 to Flannagan et al. None of these patents discloses or suggests the novel features of the present invention.
SUMMARY OF THE INVENTION
This invention addresses the conversion of small ECL level signals to CMOS level (typically 5 volt or greater) signals with the highest possible speed and drive capability. The basic approach in the invention is to keep the circuitry simple with as few parts as possible, since generally, the fewer the number of parts, the faster the circuit will be.
Briefly, a differential pre-amplifier with constant current source is used to dynamically sink and source current in the two legs of the amplifier based on the ECL signal levels at the input of the amplifier. In order to achieve the highest possible speed, the load capacitance at the output of the differential pre-amplifier is kept as small as possible. This is accomplished by designing the first stage inverters or other form of buffers, which are driven by the differential pre-amplifier, with the smallest possible geometries on the integrated circuit;. Drive capability is then provided by means of an additional buffer which may take the form of an inverter.
In an embodiment, circuit speed is addressed by biasing the input to the first inverter stage, driven by the output of the differential pre-amplifier, at a DC level at the trip point of the inverter. Since only a small voltage swing around this DC level can cause the inverter's output to switch between the V
d
and V
s
CMOS voltage levels, the speed of the circuit is increased. The desired low capacitance level at the input to this first inverter stage is achieved by designing the stage using the minimum device geometry consistent with the particular set of design rules being used. Since the first stage inverter is designed with minimum geometries, however, a second stage inverter is needed with larger geometries in order to meet the desired drive requirements. The minimization of the capacitive loading on the differential pre-amplifier, the biasing of the first stage inverter or buffer at its trip point, and the use of additional buffers or inverters to provide adequate drive capability provide a uniquely fast and powerful converter.


REFERENCES:
patent: 4906871 (1990-03-01), Iida
patent: 5463332 (1995-10-01), Yee et al.
patent: 5754059 (1998-05-01), Tanghe et al.

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