Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Bipolar transistor
Reexamination Certificate
1999-06-11
2001-04-10
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Bipolar transistor
C326S126000, C326S018000
Reexamination Certificate
active
06215330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential logic family and more particularly to a low voltage, high speed, differential logic family formed from bipolar or field effect transistors, configured for relatively low voltage operation which provides relatively reduced power consumption and part count relative to known differential logic families.
2. Description of the Prior Art
Various logic families are known for performing standard Boolean logic functions, such as AND, OR, NOT, exclusive OR functions, as well as non-Boolean functions, such as storage and buffering. Both bipolar and metal oxide semiconductor (MOS) logic families are known. An example of a bipolar logic family is transistor - transistor - logic (TTL). An example of MOS logic family is complementary metal oxide semiconductor (CMOS) logic. Bipolar logic circuits are known to have relatively high speed but suffer from relatively high power consumption. CMOS logic circuits are known to have relatively low power consumption but are relatively slower than bipolar logic families.
In order to further increase the switching speeds of bipolar logic devices, emitter coupled logic (ECL) circuits have been developed. Examples of ECL logic circuits are disclosed in U.S. Pat. Nos. 4,737,664; 4,760,289; 4,714,841; 4,751,404; 5,065,050; 5,250,860; 5,610,539 and 5,684,416. Such ECL circuits, also known as current mode logic (CML) circuits, normally include one or more pairs of differentially connected transistors with the emitters tied together forming differential pairs. Inputs are applied to the base terminals of the differential pair. The collectors of the bipolar transistors forming the differential pair are known to be connected to load resistors while the emitters are connected to a constant current source. In order to maintain a relatively fast switching speed, the collectors of the differential pair are generally buffered from the load and used to drive interstage buffers, configured as static emitter followers, which, in turn, are known to each be connected to a constant current source. Even though such ECL logic circuits are known to provide relatively high speed operation since the bipolar transistors used in these logic families are not saturated, the constant current sources in the output stage result in relatively high power consumption.
Another consideration of CML logic families is the operating voltage level of the device. In order to accommodate multiple inputs, multiple levels of differential pairs are known to be connected in a cascode or “stacked” configuration, for example, as disclosed in U.S. Pat. No. 5,075,574. Unfortunately, the operating voltage puts constraints on the number of levels in the circuit. The minimum supply voltage is the sum of all stacked base-mitter voltages (VBE, with VBE=VCE) and the voltage across the current source element (VCS), which can be an active current source in the form of a BJT with emitter degeneration resistor, or a passive device in the form of a resistor. For example,
FIG. 1
of the '574 patent illustrates a three level circuit in a cascode configuration which requires a 5.0 supply voltage. In order to reduce the supply voltage requirement, the number of levels or stacked VBE's of the circuit need to be reduced. In order to maintain the same number of inputs with fewer levels, multiple inputs are connected to the differential pair by way of input diodes, such as Schottky barrier diodes, for example, as illustrated in
FIG. 2
of the '574 patent.
FIGS. 3 and 4
of the '574 patent illustrate multiple level differential logic circuits. In particular,
FIG. 3
illustrates a silicon three level differential logic circuit for use with a 3.4 volt supply voltage.
FIG. 4
of the '574 patent illustrates the use of Schottky barrier diodes at the bases of the differential pair to further reduce the power supply voltage requirement to 3.0 volts. Since the input diodes introduce a voltage drop, input diodes are connected to both bipolar transistors forming the differential pair to balance the DC operating point of the differential pair. Such a configuration increases the part count and thus the complexity of the device.
As mentioned above, known ECL logic circuits offer the highest switching speed but unfortunately require interstage buffers with constant current sources. These constant current sources result in relatively high power consumption of the device. In addition, known ECL gate circuits, configured for lower voltage and multiple input operation, require input diodes connected to both bipolar transistors forming the transistor pair, thus increasing the part count and power consumption of such circuits. Thus, prior art is improved by reducing power consumption and complexity in which the gate circuits utilize fewer input diodes and biasing resistors relative to other logic families.
SUMMARY OF THE INVENTION
The present invention relates to a relatively low voltage, high speed, differential diode transistor logic (DDTL) family of circuits for performing various Boolean logic functions, such as AND, OR, etc. as well as non-Boolean functions, such as buffering and storage. The logic family may be configured in emitter coupled logic (ECL), also known as current mode logic (CML), with bipolar transistors, such as bipolar junction transistors (BJT) or heterojunction bipolar transistors (HBT), or source-coupled field effect transistor logic (SCFL) and utilize FETs, MOSFETs, HEMTs and MESFETs. In accordance with one aspect of the invention, gate circuits configured for reduced voltage multiple input operation only include input diodes connected to one of the transistors forming the differential pair, thus reducing the number of input diodes by one half. However, in such gate circuits in order to maintain a balanced DC operating level, a level shifting device, for example, a diode, is connected to one of the transistors within the differential pair. In accordance with another aspect of the invention in order to reduce the power consumption of devices in the logic family, a push-pull buffer which utilizes a single current source is provided in the output stage. The push-pull buffer includes a pair of output transistors defining two legs acting as a phase splitter. The collector nodes of the differential pair drive the output transistors. The push-pull circuit also includes a current steering pair of transistors. The emitter nodes of the differential pair drive the current-steering transistors which, in turn, have their emitters connected to a single constant current source. The outputs of the current-steering transistors bias the output transistors such that more current is steered to the output transistor that is at logic low, while removing current from the output transistor that is at logic high. Since the current steering action is controlled by the logic signal itself, push-pull operation is achieved. This results in improved signal transition times with reduced power consumption. An additional improvement is achieved by an enhanced clock switching circuit.
REFERENCES:
patent: 3446989 (1969-05-01), Allen et al.
patent: 3742250 (1973-06-01), Kan
patent: 4112314 (1978-09-01), Gani et al.
patent: 4378508 (1983-03-01), Scavuzzo
patent: 4513283 (1985-04-01), Leininger
patent: 4605871 (1986-08-01), Price et al.
patent: 4633104 (1986-12-01), Mallinson
patent: 4714841 (1987-12-01), Shoji et al.
patent: 4737663 (1988-04-01), Varadarajan
patent: 4737664 (1988-04-01), Wilhelm et al.
patent: 4751404 (1988-06-01), Yuen
patent: 4760289 (1988-07-01), Eichelberger et al.
patent: 4845387 (1989-07-01), Ovens
patent: 4868423 (1989-09-01), Abdi
patent: 4922135 (1990-05-01), Mollier et al.
patent: 5065050 (1991-11-01), Fernandez
patent: 5075574 (1991-12-01), Boudon
patent: 5155387 (1992-10-01), Fletcher et al.
patent: 5212409 (1993-05-01), Moulton et al.
patent: 5220212 (1993-06-01), Sinh
patent: 5250856 (1993-10-01), Burton et al.
patent: 5250860 (1993-10-01), Chu et al.
patent: 5315176 (1994-05-01), Popescu
Auduong Gene N.
Nelms David
TRW Inc.
Yatsko Michael S.
LandOfFree
Differential diode transistor logic (DDTL) circuit enhancements does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Differential diode transistor logic (DDTL) circuit enhancements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Differential diode transistor logic (DDTL) circuit enhancements will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2490764