Differential delay-line

Details Differential delay-line Differential delay-line

2007-01-02

2007-01-02

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C324S1540PB, C327S565000

Reexamination Certificate

active

10897745

ABSTRACT:
A printed circuit board is built including metal traces for a differential clock. Within a break in each metal trace pads for a delay line socket are included along with pads for two 0-ohm resistors in series. In between the two 0-ohm resistors metal traces are build in a configuration to provide a specified delay in a signal passing through the trace. This group of pads and traces allows a designer to test (on the completed printed circuit board) differential clocks in modes including negative skew. In normal operation, the 0-ohm resistors are present on the printed circuit board and the clock signals pass through the metal traces build in a configuration to provide a specified delay in the signals passing through the traces. During testing, delay lines may be placed in the delay line sockets and the 0-ohm resistors may be removed. When 0 ns delay lines are placed in the sockets, the clock delays are negatively skewed from normal delay since the clock signals no longer pass through the long metal traces between the 0-ohm resistors.

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