Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-07-17
2002-11-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S068000
Reexamination Certificate
active
06476642
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to differential current driver circuits and, more particularly, to improved differential current driver circuits for use in accordance with data busses.
BACKGROUND OF THE INVENTION
The need for high speed busses that meet both packet data communications and telecommunications requirements is an important current area of research in electronic switching systems. Systems that can integrate these different types of data cost effectively have an advantage in the market place. Few existing switching systems have even come close to providing cost effective integrated transport (let alone switching) of these types of data. One means of achieving a cost effective switching system for both telecommunications and packet data switching is the use of a synchronous bus. Early synchronous busses suffered from high cross-talk on their signals and therefore newer bus designs have resorted to the use of differential signal paths.
Most differential signal systems are implemented with a logic family known as Emitter Coupled Logic (ECL). These systems were unable to scale to high data rates (above 100 mega-transfers per second) due to a variety of problems. Some of the problems with existing differential switching backplanes based on ECL include: (i) the use of ECL gives rise to a lower backplane impedance due to low driver output impedance; (ii) the use of ECL does not provide any sort of wired-OR function on the backplane for functions such as arbitration; (iii) the use of ECL gives rise to spurious wave propagations when going into high impedance (bus isolation) mode; and (iv) the use of ECL gives rise to an unbalanced wave propagation when going into its signal drive mode from high impedance.
These and other problems necessitated the invention of new differential signal driver logic. Such differential signal driver logic is described in U.S Pat. No. 5,430,396, issued to D. A. Morano on Jul. 4, 1995 and entitled “Backplane Bus for Differential Signals,” and in U.S. Pat. No. 5,450,026, issued to D. A. Morano on Sep. 12, 1995 and entitled “Current Mode Driver for Differential Bus,” the disclosures of which are incorporated by reference herein. Such differential signal driver logic is generally referred to as D
2
L or Dave's Differential Logic (after the inventor of the previous patents and the present invention).
Particularly, U.S Pat. No. 5,430,396 discloses a differential voltage bus system wherein the two leads of the bus are biased by the termination networks with a predetermined voltage difference representing a digital signal of one binary type. The bus driver in each bus master connects a current source to one of the two bus leads and a current sink to the other of the two bus leads in response to an input digital signal of the other binary type thereby changing the voltage difference on the bus to represent the other binary type. In response to an input digital signal of the first-mentioned binary type, the bus driver isolates the current source and sink from the bus and connects them together in order to decrease the detrimental effect of transients. The selective switching in the bus driver is performed by MOSFET (metal oxide semiconductor field effect transistors) switches that are driven by buffer driver circuits each of which uses a combination of MOSFETs and an NPN transistor to drive its respective MOSFET switch with a high peak current thereby enabling rapid switching. The current source and sink in the bus driver also uses a combination of MOSFETs and NPN transistors in order to permit operation of the bus at low voltage levels.
U.S. Pat. No. 5,450,026 discloses a current mode bus driver which couples input digital signals to a bus which is normally biased with a voltage difference representing one binary type. The current mode bus driver responds to input digital signals of the other binary type by connecting a current source to one lead of the bus and a current sink to the other lead of the bus, thereby driving the bus to a voltage difference which represents the other binary type. In response to input digital signals of the first-mentioned binary type, the bus driver isolates the current source and current sink from the bus and connects the current source directly to the current sink. The selective switching is performed by n-channel MOSFETs that are driven by the input digital signals through unique buffer driver circuits employing a CMOS (complementary metal oxide semiconductor) inverter, an n-channel MOSFET and an NPN transistor. A combination of MOSFETs and NPN transistors provide a current source and sink that permit operation of the bus at very low voltage levels.
Such interface logic solves a number of problems related particularly to high speed busses for telecommunications applications. An ideal representation of what a D
2
L driver circuit must emulate is shown in FIG.
1
A. Specifically,
FIG. 1A
shows the basic idea involved in D
2
L bus driving technology. As can be seen in the figure, it is basically a controlled current source
10
with two output states whose value can be switched from an input (not shown) to the driver. The two output current values are zero Amperes and some other non-zero value. Most circuits to date have used the value of 10 milliAmperes and the currently described circuit preferably does also. This is the most used non-zero output current used so far in applications.
Ideally, the output impedance approaches infinity but any output impedance that is sufficiently larger than the bus characteristic impedance is quite useful. Of course, the higher the output impedance is, the better the performance of the circuit. Practical D
2
L circuits to date still have a lower output impedance than might be desirable but, as will be explained herein, the circuit of the present invention has an improved output impedance, i.e., higher output impedance.
Referring to
FIG. 1B
, the use of D
2
L driver circuitry in one of its major applications is shown. A bidirectional bus
10
is shown with two bus masters (Bus Master
1
and Bus Master
2
). Terminations
16
are shown on each end of the bidirectional bus
10
. Each bus master is composed of a D
2
L driver circuit and a corresponding receiver circuit. The receiver circuit is any differential receiver suited to the D
2
L signal characteristics on the bus. As shown, Bus Master
1
includes a D
2
L driver circuit
12
-
1
and a receiver circuit
14
-
1
, while Bus Master
2
includes a D
2
L driver circuit
12
-
2
and a receiver circuit
14
-
2
. Each D
2
L driver circuit takes as its primary input a binary signal, e.g., a CMOS (complementary metal oxide semiconductor) input, and produces on its output two signals that are connected to the two leads of the bus (BUS+ and BUS− as depicted in FIG.
1
A). Each of the output signals may source equal but opposite currents in response to the binary input signal of one type and will not source any current in response to a binary signal of the other type. Multiple D
2
L drivers may also be used in parallel for each bus master with a corresponding bus of parallel pairs of leads.
Although the invention of early D
2
L systems solved many of the problems discussed previously, with regard to the use of ECL for example, most existing D
2
L drivers can be difficult to use because of poor electrical performance and poor temperature stability. An example of an existing integrated circuit (IC) that uses the D
2
L signaling system is the BLAST (Balanced Logic And Synchronous Transceiver) I integrated circuit. This was a BiCMOS design and suffered from the problems listed above.
Some of the problems with existing D
2
L drivers are: (i) there is not a precise enough balance between the high and low output currents; (ii) the high and low output currents vary with different bus termination voltages; (iii) the driver exhibits poor temperature stability over the full commercial temperature range; (iv) early cheap CMOS-only designs were unusable due to poor performance; (v) existing BiCMOS (bipolar CMOS) designs are costly
Agere Systems Guardian Corp.
Cho James H
Ryan & Mason & Lewis, LLP
Tokar Michael
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