Differential clock ganging

Details Differential clock ganging Differential clock ganging

2008-03-18

2008-03-18

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11171576

ABSTRACT:
Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect output pins for differential clock signals with termination resistors. The pattern of conductors comprises a group of conductors for a positive clock (p-clock) signal and a group of conductors for a negative clock (n-clock) signal. The conductors for the p-clock signal intersect at a gang point between the output pins and pads for the termination resistors. Similarly, the conductors for the n-clock signals intersect at a gang point between the pins and the pads. In many embodiments, the distance between the pins and pads may be approximately 120 mils. In further embodiments, the distance may be longer or shorter than 120 mils. Other embodiments are disclosed and claimed.

REFERENCES:
patent: 6937078 (2005-08-01), Schrodinger
patent: 7126366 (2006-10-01), Ohashi et al.
Katrai, Cameron , “Managing Clock Distribution and Optiizing Clock Skew in Networking Applications”,PERICOM; Application Note 14, (Dec. 29, 1998), pp. 71-78.

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