Differential circuit, output buffer circuit and...

Details Differential circuit, output buffer circuit and... Differential circuit, output buffer circuit and...

2006-07-13

2008-11-25

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S065000, C327S563000

Reexamination Certificate

active

07456662

ABSTRACT:
An output buffer circuit includes: a differential circuit; and first and second load circuits coupled between the differential circuit and a high power supply voltage VDDH. Such a differential circuit includes first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above a maximum gate-body voltage VgbMAX (where VDDH>VgbMAX), respectively. Body electrodes & source electrodes are coupled to a common node. Gate electrodes are coupled to first and second differential input signals, respectively, such that voltages on drains of the first and second NMOS transistors represent results of a differential switching operation, respectively. More particularly, the drains of the first and second NMOS transistors are coupled to the first and second loads. The common node is coupled to a bias voltage such that Vgb of the first & second NMOS transistors is VgbMAX≧Vgb.

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