Differential bipolar stray-insensitive pipelined...

Details Differential bipolar stray-insensitive pipelined... Differential bipolar stray-insensitive pipelined...

2001-12-04

2003-06-24

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000

Reexamination Certificate

active

06583743

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
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STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK
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BACKGROUND OF THE INVENTION
A digital-to-analog converter (DAC) is a device for generating an analog output (usually a voltage or current) that is a representation of a sequence of bits at its input. For example, an 8-bit DAC outputs a voltage or current that can have one of 256 different values. So if the output ranges from 0 to 10V, the DAC outputs a voltage corresponding to one of 256 voltage levels between 0 and 10V. A number of techniques are used to implement this conversion.
One such technique is known as an algorithmic DAC, which is based on a step-by-step method. Generally, a multi-bit word, or digital input, is processed one portion at a time. In each step, a partial result from the previous step is combined with a portion of the multi-bit input word and then passed on to the next step.
FIG. 1
is a flowchart illustrating the steps involved in the basic algorithmic DAC. The input word is processed one bit at a time, starting from the least significant bit. An interim value R is initialized to zero. A counter n, used to count the number of bits processed, is also initialized to zero. A loop commences wherein if a bit b
n
is 0, the interim value R is divided in half. If the bit b
n
is 1, the sum of the interim value R and a reference voltage V
ref
is divided in half. The value of the counter n is increased by one. The loop is repeated for the next-most significant bit until n=N, where N is the total number of bits in the word input. At that point, the interim value R represents an analog form of the word input. Dividing R in half weights the digital bits according to their significance. That is, the least significant bit has the smallest impact on the outcome of the DAC since it will be divided more times than any of the other bits.
Although there are other algorithms available in the art, the above technique is attractive because of the savings it offers in terms of circuit size and power. Two architectures that have been developed to implement this technique are the pipelined DAC and the cyclic DAC. The pipelined DAC provides operating speed at the expense of size and, therefore, power. The cyclic DAC is more economical than the pipelined DAC since it reuses the same hardware for each iteration of the algorithm. However, the reduction in size of the cyclic DAC comes at the expense of a lower output rate. It is most suitable to implement algorithmic DACs using a switched-capacitor (SC) technique; however, other techniques such as switched-current (SI) can also be used.
FIG. 2A
illustrates a SC quasi-passive pipelined DAC (QPPDAC), represented generally by the numeral
10
that is described below. (Originally, SC pipelined DACs used an operational amplifier (op amp) in each stage for performing the required operations; however, this made the DAC very expensive.) The DAC is referred to as quasi-passive because no op amps are used for performing the required operations. Rather, the DAC essentially comprises capacitors and switches.
The QPPDAC circuit
10
includes a series of stages
12
. Each stage
12
comprises a capacitor
14
and several switches. A first plate (herein referred to as the bottom plate for illustrative purposes only) of the capacitor
14
is coupled to ground. A second plate (herein referred to as the top plate for illustrative purposes only) of the capacitor
14
is coupled to a reference voltage V
ref
via a first switch
16
and to ground via a second switch
18
. The top plate of the capacitor
14
is also coupled to the top plate of the capacitor in a previous stage via a third switch
20
. For the first stage
12
a
, there is no previous stage for the top plate of the capacitor
14
to be coupled. Instead, the top plate of the capacitor
14
is coupled via the third switch
20
to the top plate of an initialization capacitor
22
, and an initialization switch
24
. The initialization capacitor
22
has the same capacitance as the remaining capacitors
14
. Both the bottom plate of the initialization capacitor
22
and the other end of the initialization switch
24
are coupled to ground. For the final stage
12
f
, the capacitor
14
f
is further coupled to an output stage such as sample and hold (not shown).
FIG. 2B
shows a timing diagram for the QPPDAC. The QPPDAC uses a three-phase clock for timing. The clock phases run continuously; that is, no reset cycle or the like is necessary, and a portion of a new digital input word is taken in every clock cycle. Also, the phases are staggered in time and do not overlap. Therefore, the DAC can operate on (N div 3) words at the same time, where N is the number of resolution bits of the DAC and the portion of the word taken in is three (3) bits in size.
FIG. 3
provides an illustrative example as to how the bits are input into the QPPDAC, represented generally by the numeral
30
. In this example, N=9, so three numbers can be converted at a time. In a first clock cycle, three bits from each of three words are input to the DAC
32
. These bits are the least significant bits (LSB) of word
3
, the middle 3 bits of word
2
, and the most significant bits (MSB) of word
1
. The less significant bits of word
1
and word
2
have already been converted in previous clock cycles. In the next clock cycle, the middle three bits of word
3
, the MSB of word
2
, and the LSB of a new word, word
4
, are converted. Lastly, in the next clock cycle, the MSB of word
3
, the middle three bits of word four, and the LSB of a new word, word
5
, are converted. Therefore, after 3 clock cycles, an entire 9-bit word is converted.
Referring once again to
FIG. 2A
, b
j
[k] represents the j-th bit of the k-th digital input word. The conversion process for each word begins with the LSB. Depending on the bit value, either the first switch
16
a
(S
0,1
) or the second switch
18
a
(S
0,2
) is closed during the first phase of the clock cycle, &phgr;
1
. If the first switch
16
a
is closed, C
0
is charged to V
ref
. If the second switch
18
a
is closed, C
0
is grounded. Therefore, the voltage at C
0
can be represented as b
0
[m]V
ref
, where b
0
is 1 or 0. At the same time, the initialization switch
24
is closed and the initialization capacitor
22
is discharged to ground. The third switch
20
a
remains open and closes only in the following clock phase.
In the second phase, &phgr;
2
, of the same clock cycle, the first switch
16
a
and second switch
18
a
in the first stage
12
a
are opened and the third switch
20
a
closes. C
0
shares its charge with the initialization capacitor
22
through the third switch
20
a
. Since all the capacitors are matched, the voltage at C
0
is equal to:
V
C
0
=(
b
0
[m]V
ref
)/2
During the same phase of the same clock cycle &phgr;
2
, C
1
is charged to b
1
[m]V
ref
, where b
1
is 1 or 0.
In the third phase, &phgr;
3
, of the same clock cycle, the third switch
20
a
in the first stage
12
a
opens. Also, the first switch
16
b
and the second switch
18
b
in the second stage
12
b
are opened and the third switch
20
b
closes. Therefore, the voltage across C
1
and C
0
is shared. Again, since the capacitors are matched, the voltage will divide equally across C
1
and C
0
. Therefore, at the end of the third phase of the clock cycle, &phgr;
3
, the voltage across C
1
is:
V
C
1
=
1
2
⁢
b
1
⁡
[
m
]
⁢
V
ref
+
1
4
⁢
b
0
⁡
[
m
]
⁢
V
ref
At the same time, that is during &phgr;
3
of the same clock cycle, C
2
is charged to b
2
[m]V
ref
, where b
2
is 0 or 1.
The next phase is the first phase, &phgr;
1
, of the next clock cycle. The first three stages behave as described above. The fourth stage
12
d
continues to convert the same word. The third switch
20
b
in the second stage
12
b
opens. Also, the

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