Differential and hierarchical sensing for memory circuits

Details Differential and hierarchical sensing for memory circuits Differential and hierarchical sensing for memory circuits

2007-10-23

2007-10-23

Phan, Trong (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S203000, C365S230050, C365S205000

Reexamination Certificate

active

11190542

ABSTRACT:
A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

REFERENCES:
patent: 6278647 (2001-08-01), Saitoh et al.
patent: 6621758 (2003-09-01), Cheung et al.
patent: 6687148 (2004-02-01), Shau
patent: 6977860 (2005-12-01), Tooher et al.
patent: 7054178 (2006-05-01), Shiah et al.

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