Differential amplifier in a memory data path

Details Differential amplifier in a memory data path Differential amplifier in a memory data path

1995-03-01

1997-07-15

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365196, 365205, 365220, 365221, B11C 506

Patent

active

056489277

ABSTRACT:
A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

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Kazutami Arimoto, et al., A 60-ns 3.3-V-Only 16-Mbit DRAM with Multipurpose Register, IEEE Journal of Solid-State Circuits, vol., 24, No. 5, Oct. 1989, pp. 1184-1190.
Toshio Yamada, et al., A 4-Mbit DRAM with 16-bit Concurrent ECC, IEEE Journal of Solid-State Circuits, vol., 23, No. 1, Feb. 1988, pp. 20-26.

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