Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-08-31
2002-10-29
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
Reexamination Certificate
active
06472289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dielectrically separated wafer and a fabrication method for the same, and particularly relates to a dielectrically separated wafer provided with dielectrically separated silicon islands having a N on N+ or a P on P+ structure with different dopants at different depths, to suppressing the growth of voids (gaps) when the polysilicon layer is grown on the surface of a dielectrically separating oxide film, and to flattening the surface between one dielectrically separated silicon island and another dielectrically separated island.
2. Description of the Related Art
A laminated dielectrically separated wafer is known as one type of laminated silicon wafer. The conventional laminated dielectrically separated wafer is fabricated by each of the processes shown in FIG.
15
.
FIG. 15
shows the cross-sectional structure of the dielectrically separated wafer fabricated by this method.
First, a silicon wafer is prepared whose active layer surface is mirror polished (FIG.
15
(
a
)). Either an N-type or a P-type can be used. Next, a mask oxide film
11
is formed on the surface of this silicon wafer (FIG.
15
(
b
)). Furthermore, a photoresist
12
is attached to the oxide film, and by photolithography windows are formed at specified locations. Additionally, the oxide film
11
exposed in these windows is eliminated, and windows having a specified pattern are formed on the oxide film. As a result, one part of the surface of the silicon wafer
10
is exposed. Next, after removing the photoresist
12
, this silicon wafer
10
is immersed in an alkaline etchant, and the surface of the wafer. undergoes anisotropic etching (FIG.
15
(
c
)).
In this manner, dielectrically separating grooves
13
having a v-shaped cross-section are formed on the wafer surface.
Moreover, in this context, anisotropic etching is etching whose etching speed in the vertical direction is larger than the horizontal direction, and thus is directionally dependent due to the crystalline orientation of the silicon wafer
10
.
Next, the mask oxide film
11
is cleaned and removed using a dilute HF solution (dilute hydrofluoride solution) or a buffer hydrofluoride solution (FIG.
15
(
d
)). Subsequently, the dielectrically separating oxide film
14
of a specified thickness is formed on the silicon wafer surface, including the dielectrically separating grooves
13
.
Next, the surface of this silicon wafer
10
, that is, on the dielectrically separated oxide surface
14
, a high temperature polysilicon layer
16
is grown to a specified thickness by the high temperature CVD method, at approximately 1200°~1300° C. (FIG.
15
(
f
)). Next, the peripheral portion of the wafer is chamfered, and as necessary, the undersurface of the wafer is flattened. Next, the high temperature polysilicon layer
16
of the wafer surface is cut and polished to a thickness of approximately 10~80&mgr;.
In addition, as necessary, subsequently a low temperature polysilicon layer
17
having a thickness of 1~5&mgr; is formed on the wafer surface by the lower temperature CVD method at approximately 550~700° C., and the surface of the low temperature polysilicon layer
17
is polished in order to produce a mirror surface on the laminated surface.
In contrast, a silicon wafer
20
that serves as the support substrate wafer is prepared separately (FIG.
15
(
h
)). The surface of this wafer is mirror polished. Next, the mirror surface of the silicon wafer
10
is brought into contact with and laminated on the mirror surface of the silicon wafer
20
(FIG.
15
(
i
)).
Subsequently, a specified annealing is carried out in order to increase the lamination strength of these laminated wafers.
Next, as shown in FIG.
15
(
j
), the peripheral portion of the active surface wafer of these laminated wafers is chamfered. In addition, the laminated wafer having the active surface is ground and polished. The amount of grinding of this active surface wafer exposes to the outside a part of the dielectrically separating oxide film
14
, and on the surface of the high temperature polysilicon surface
16
, dielectrically separated silicon islands
30
defined by the dielectrically separating oxide film
14
are realized.
Three problems are encountered in the conventional dielectrically separated wafers. The first problem is related to the restricted surface area for manufacturing the semiconductor device on the dielectric separated wafer; the second problem is related to a void (gap) B, which is an air bubble defect, will develop between the neighboring polysilicon cores; and the third problem is related to the surface steps caused by the differences of the grinding speed of the constituting layers. These three problems will be described hereinafter.
The first problem will be described. In recent years, the power IC for a large electric current has been developed. In the power IC, a dielectrically separated structure wherein each element is completely separated by a dielectrically separating oxide film has been adopted. In these elements, in order to sustain well the falling voltage of the PN junction, it is necessary to make the specific resistance of the dielectrically separated silicon islands very high.
However, a high specific resistance limits the voltage of the elements during operation, incurring the disadvantage of increasing what is termed the operational resistance.
Thus, generally, between the dielectrically separated silicon islands and the dielectrically separating oxide film a high concentration impurity layer (N+ region and P+ region) is provided in which impurities are diffused in high concentration. This high concentration impurity layer serves as the path for the current and reduces the increase in operational resistance.
In this type of dielectrically separated wafer, conventionally, as shown in
FIG. 16
, the high concentration impurity layer
30
a
is formed along the dielectrically separating oxide film
14
having a saucer shape, and on the inside of this high concentration impurity layer
30
a
a low concentration impurity layer
30
b
is defined.
In order to fabricate this dielectrically separated wafer, first the surface of a silicon wafer having a low concentration of impurities (dopants) undergoes anisotropic etching, and dielectrically separating grooves are formed. Subsequently, over the entire surface of the silicon wafer on which the dielectrically separating grooves have been formed, a high concentration impurity layer
30
a
is formed at a specified depth by thermally diffusing or ion implanting a dopant having the same conductivity. Subsequently, the dielectrically separating oxide film
14
, etc., are formed, and further, as described above, by grinding and polishing the undersurface of the wafer, dielectrically separated silicon islands
30
having a N on N+ structure or a P on P+ structure are realized on the wafer surface.
However, because the high concentration impurity layer of the dielectrically separated wafer according to this type of conventional technology has a saucer shaped surface cross-section, like the dielectrically separating oxide film, the peripheral portion of the surface of the dielectrically separated silicon islands is structured by a high concentration impurity layer.
As a result, first problems arise that it is necessary to manufacture a device avoiding the regions of this exposed high concentration impurity layer, and the fabrication surface area of the device at the dielectrically separated silicon islands becomes small.
Next, the second problem will be described. As described before, the conventional laminated dielectrically separated wafer is fabricated by each of the processes shown in FIG.
15
. However, according to the conventional fabrication method of the dielectrically separated wafer, during the growth period of the polysilicon layer
16
by the high temperature CVD method, as shown in
FIG. 15
, in the case that there exists a particle P, a defect, etc., on the surface of the dielectr
Oi Hiroyuki
Sato Kazuya
Shimamura Hiroshi
Hoang Quoc
Mitsubishi Materials Silicon Corporation
Nelms David
Pillsbury & Winthrop LLP
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