Dielectrically isolated semiconductor substrate

Details Dielectrically isolated semiconductor substrate Dielectrically isolated semiconductor substrate

1989-03-30

1989-11-07

Hearn, Brian E.

Metal treatment

Barrier layer stock material, p-n type

With non-semiconductive coating thereon

357 60, 437976, 437974, 437 62, 437921, 148DIG17, 148DIG159, H01L 21265

Patent

active

048789577

ABSTRACT:
A dielectrically isolated semiconductor wafer substrate includes first and second semiconductive layers bonded to each other by a direct bonding technique in such a manner that an insulative layer is sandwiched therebetween. The first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, while the second semiconductive layer is a second silicon layer having a (111) crystal surface orientation. Thereafter, a peripheral portion of the resultant substrate is removed, and a substrate of a slightly smaller size is obtained which is provided with an additionally formed new orientation flat.

REFERENCES:
patent: 4638552 (1987-01-01), Shimbo
patent: 4774196 (1987-09-01), Blanchard
Brooks, A. D., Donovan, R. P. "Low-Temperature Electrostatic Silicon-to-Silicon Seals Using Spittered Borosilicat Glass". J. Electrochem. Soc.: Solid State Science and Technology, Apr. 1972.

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