Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a

Details Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a

1987-04-02

1988-06-14

Carroll, James J.

357 4, 357 231, 357 42, 357 43, 357 49, 357 55, 357 56, 357 80, H01L 2702, H01L 2906, H01L 2978

Patent

active

047515619

ABSTRACT:
A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

REFERENCES:
patent: 3865649 (1975-02-01), Beasom
patent: 4127860 (1978-11-01), Beelitz et al.
patent: 4299024 (1981-11-01), Piotrowski
patent: 4385937 (1983-05-01), Ohmura
patent: 4481707 (1984-11-01), Cunniff
patent: 4609407 (1986-09-01), Masao et al.

Affiliated with

Also associated with

Rating

Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-508320