High speed low power MOS buffer circuit for converting TTL logic

Details High speed low power MOS buffer circuit for converting TTL logic High speed low power MOS buffer circuit for converting TTL logic

1982-11-01

1985-01-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307453, 307579, 307279, H03K 19096, H03K 17284, H03K 17693

Patent

active

044968574

ABSTRACT:
MOS semiconductor address buffer for converting TTL logic states to a MOS logic state requiring only a single clock and having improved power efficiency. The address buffer operates in response to the single clock pulse to set a latch and connect the latch to output drives for providing complementary MOS logic levels.

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