Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-29
2001-05-01
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06225664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit having dielectric isolation regions, which switches at a high speed, and more particularly, an IC driver capable of driving output power devices operating with a high breakdown voltage or a high blocking voltage at the high speed. The present invention also relates to a power integrated circuit (referred to as “power IC” hereinafter) merging output power devices and driver/controller for driving/controlling the output power devices in a same semiconductor chip, the chip having dielectric isolation regions, the power IC operating with a high breakdown voltage or a high blocking voltage at the high speed.
2. Description of the Related Art
A semiconductor integrated circuit—using SOI structure where a supporting substrate
1
, a buried insulation film (SOI oxide film)
12
, and Si films
140
,
147
,
139
,
138
,
137
are stacked beginning from the bottom as shown in FIG.
1
—is characterized by an easiness for accomplishing a high breakdown voltage or high blocking voltage performance. The SOI semiconductor integrated circuit has the further advantages of small parasitic capacitance of respective integrated elements and an excellent adaptability to the high speed operation. Moreover, if Si films
140
,
147
,
139
,
138
, and
137
are made thinner, the SOI structure can suppress the short channel effect of semiconductor devices such as MOSFET (MOS Field Effect Transistor) disposed in the Si film
147
or the like and adopt a finer and finer structure, accomplishing higher integration densities. Usually, the semiconductor integrated circuit having SOI structure is composed by dielectric isolation region of Si films
140
,
147
,
139
,
138
,
137
formed on the SOI oxide film
12
into a plurality of islands
140
,
147
,
139
,
138
,
137
by element isolation regions composed of a trench side wall oxide film
6
and a buried trench polycrystalline silicon
7
.
FIG. 1
shows a dielectrically isolated (referred as “DI” hereinafter) integrated circuit of BiCMOS structure wherein a pMOS transistor composed of p
+
source region
141
and p
+
drain region
142
is disposed in the island
147
of Si, an nMOS transistor composed of n
+
source region
511
and n
+
drain region
512
in the island
139
of Si and an npn bipolar transistor composed of n
+
injector region
601
, p base area
602
and n
+
collector region
602
in the island
138
of Si. The nMOS transistor is disposed in a p well
501
and p
+
contact region
512
is disposed in the p well
501
. On the other hand, n
+
contact region
143
is disposed in the island
147
of Si.
In the field of power semiconductor device (power device), a DI integrated circuit driver as shown in
FIG. 2
is well known. In general, by such DI integrated circuit driver, an output power device unit external to the IC driver is driven.
FIG. 2
shows a DI integrated circuit driver, called “half-bridge driver”. Particularly when a high breakdown voltage or high blocking voltage is required for the output power device unit, the output power device unit is composed by serial connection of an upper-side output power device Q
u1
and a lower-side output power device Q
d1
, and this output power device unit is driven by a half bridge driver, as shown in FIG.
2
. In this case, one main electrode of the upper-side output power device Q
u1
is connected to a positive high level power supply
101
while one main electrode of the lower-side output power device Q
d1
to a ground potential (GND). The other main electrode of the upper-side output power device Q
u1
and the other main electrode of the lower-side output power device Q
d1
are connected to a neutral point terminal N
n1
, while this neutral point terminal N
n1
is connected to a load not illustrated.
As shown in
FIG. 2
, the upper-side output power device Q
u1
is driven by an upper-side driver
102
in “a floating state”. In other words, an output terminal N
u1
of the upper-side driver
102
of the IC driver is connected to the control electrode of the external upper-side output power device Q
u1
. On the other hand, an output terminal N
d1
of the lower-side driver
103
of the IC driver is connected to the control electrode of the external lower-side output power device Q
d1
. The upper-side driver
102
is connected between an internal power supply circuit
105
and the neutral point terminal N
n1
and supplied with an predetermined power supply voltage. On the other hand, the lower-side driver
103
is connected between a low level power supply
106
and the ground potential (GND) and supplied with an predetermined power supply voltage. An upper-side control signal from an distribution logic
104
is supplied to the upper-side driver
102
via a transistor Q
c
, while a lower-side control signal from the distribution logic
104
is supplied directly to the lower-side driver
103
.
In the semiconductor integrated circuit having SOI structure, the upper-side driver
102
, lower-side driver
103
, distribution logic
104
, internal power supply circuit
105
or the like are disposed respectively in a plurality of islands. In
FIG. 2
, an upper-side recovery diode D
u1
is connected in parallel to the nMOSFET as upper-side output power device Q
u1
and an lower-side recovery diode D
d1
to the nMOSFET as lower-side output power device Q
d1
.
FIG. 3
also is a circuit diagram showing a similar conventional IC driver. Namely, it shows more in detail the upper-side driver
102
and the lower-side driver
103
composing an IC driver. The upper-side driver
102
is composed of an upper-side CMOS inverter
111
, an upper-side buffer amp
121
and an upper-side control logic
131
, while lower-side driver
103
is composed of a lower-side CMOS inverter
112
, a lower-side buffer amp
122
and a lower-side control logic
132
.
FIG. 3
shows an example where an insulated gate bipolar transistor (IGBT) is used respectively as external upper-side output power device Q
u2
and lower-side output power device Q
d2
. An upper-side recovery diode D
u2
is connected in parallel to the upper-side output power device Q
u2
and an lower-side recovery diode D
d2
to the lower-side output power device Q
d2
.
In the circuit configuration shown in FIG.
2
and
FIG. 3
, the upper-side output power device Q
u1
, Q
u2
and the lower-side output power device Q
d1
, Q
d2
are driven by the upper-side driver
102
and the lower-side driver
103
and switched on and off alternatively. As the result, the potential of the neutral point terminal N
n1
, N
n2
repeats increase and decrease between potential levels of the ground potential (GND) and the high level power supply
101
in accordance with the alternative on and off of the upper-side output power device Q
u1
, Q
u2
and the lower-side output power device Q
d1
, Q
d2
.
FIG. 4
shows schematically the waveform of this switching state composed of these repeated increases and decreases.
FIG. 4
illustrates only the operation of 3 cycles; however, it is obvious that such cycle is repeated for a predetermined period of time. Namely,
FIG. 4
shows three outputs sections corresponding to an upper-side output O
u
at nodes N
u1
, N
u2
, a neutral output O
n
at node N
n1
, N
n2
and a lower-side output O
d
at nodes N
d1
, N
d2
of FIG.
2
and FIG.
3
. Note that inflection points of respective waveforms overlap substantially each other, while the position on the X axis of respective outputs O
u
, O
n
, O
d
is slightly displaced in
FIG. 4
for illustrative convenience. The upper-side output O
u
biases the gate of the external upper-side output power device Q
u1
, Q
u2
, while the lower-side output O
d
biases the gate of the lower-side output power device Q
d1
, Q
d2
. For the first ½ cycle, the lower-side output power device Q
d
supply a predetermined potential (gate bias) O
d
measured from the GND, while the upper-side output power device Q
u
is almost zero in respect of the neutral point outpu
Arai Haruki
Endo Koichi
Masuda Kumiko
Sato Nobuyuki
Abraham Fetsum
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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