Dielectric layers for metal lines in semiconductor chips

Details Dielectric layers for metal lines in semiconductor chips Dielectric layers for metal lines in semiconductor chips

2006-09-08

2009-10-06

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S619000, C438S622000, C438S623000, C438S687000, C438S781000, C257SE21273, C257SE21293, C257SE21576, C257SE21581, C257SE23144, C257SE23161, C257SE23167

Reexamination Certificate

active

07598166

ABSTRACT:
A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.

REFERENCES:
patent: 6159842 (2000-12-01), Chang et al.
patent: 6486077 (2002-11-01), Sato
patent: 6518130 (2003-02-01), Ohno
patent: 6958524 (2005-10-01), Li et al.
patent: 7153766 (2006-12-01), Zhang et al.

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