Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2000-12-26
2003-05-13
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S430000, C438S435000, C438S458000
Reexamination Certificate
active
06562692
ABSTRACT:
This application is the national phase of international application PCT/JP99/03297 filed Jun. 22, 1999 which designated the U.S, and that international application published under PCT Article 21(2) in English.
TECHNICAL FIELD
The present invention relates to a dielectric isolated wafer and its production process. More specifically, the present invention relates to the production method of a dielectric isolated wafer that prevents negative resist coated on the back surface of a silicon wafer from moving around to the front surface of the wafer periphery, and flooding the window of the groove for dielectric isolation formed in the negative resist on the wafer front surface present in this region, and when developing the surface negative resist film after coating this negative resist on the back surface, the vicinity of the periphery of the lower negative resist film is less susceptible to dissolution even if the developing solution moves around to the wafer back surface.
In addition, the present invention also relates to a dielectric isolated wafer and its production method that flattens depressions (level differences) in the wafer front surface that have formed due to separation polishing of a silicon island of a dielectric isolated wafer during production of a dielectric isolated wafer having a dielectric isolated silicon island.
Furthermore, the present application is based on Japanese Patent Application No. Hei 10-181084 and Japanese Patent Application No. Hei 10-181085, the contents of which are incorporated herein by reference.
BACKGROUND ART
Typical dielectric isolated wafers are produced by forming a groove for dielectric isolation on the surface of a silicon wafer, laminating a dielectric isolated oxide film on top of it, growing a polysilicon layer on the dielectric isolated oxide film to a thickness roughly equal to the thickness of the wafer by high-temperature chemical vapor deposition (CVD), and producing silicon single crystal of the dielectric isolated silicon island by grinding and polishing from the silicon wafer side.
However, in the case of dielectric isolated wafers produced by this method, wafers were only able to be produced up to a diameter of 4 inches due to considerations for total thickness and warping. Therefore, in order to solve problems encountered when trying to increase the diameter of these wafers, a laminated dielectric isolated wafer has recently been developed that is produced by laminating a dielectric isolated layer in the form of an active layer and a supporting substrate wafer that supports it.
This laminated dielectric isolated wafer is produced by going through each of the steps in the explanatory drawings of
FIGS. 5A-J
that shows the production process of typical laminated dielectric isolated wafers. The following provides an explanation of this laminated dielectric isolated wafer with reference to
FIGS. 5A-J
.
To begin with, a silicon wafer
10
, the surface of which is mirrored, is prepared for use as the active layer wafer (see FIG.
5
A). Next, mask oxide film
11
is formed on the front and back surfaces of this silicon wafer
10
(see FIG.
5
B), after which negative resist film
12
with window
12
a
is formed by photolithography. A window of a prescribed pattern is formed in oxide film
11
by means of this window to expose the upper layer of silicon wafer
10
. Next, this silicon wafer
10
is immersed in etching solution (isopropyl alcohol (IPA)/KOH/H
2
O) to perform anisotropic etching of the inside of window
12
a
of the wafer front surface (see FIG.
5
C). As a result, dielectric isolation groove
13
having a V-shaped cross-section is formed in the wafer front surface. Furthermore, the anisotropic etching mentioned here refers to etching originating in the azimuth of the crystal surface of silicon wafer
10
in which the etching speed in the direction of depth is greater than that in the horizontal direction, and the etching speed is direction-dependent.
Next, negative resist film
12
is removed and the exposed mask oxide film
11
is washed and removed with dilute HF solution (see FIG.
5
D). Subsequently, a dopant (such as Sb or As) can be thermally dispersed or ion injected into silicon wafer
10
as necessary. Dielectric isolated oxide film
14
is then formed by oxidizing heat treatment on the wafer front surface (see FIG.
5
E). As a result, dielectric isolated oxide film
14
is also formed on dielectric isolation groove
13
. Next, the front surface of this wafer is washed.
Subsequently, a seed amorphous silicon layer or seed polysilicon layer
15
is deposited on the front surface of silicon wafer
10
by low-temperature chemical vapor deposition (CVD) at about 600° C. (about 550-700° C.). After washing, high-temperature polysilicon layer
16
is grown to a thick layer on this seed amorphous silicon or seed polysilicon layer
15
by high-temperature CVD at about 1250° C. (about 1200-1300° C.) (see FIG.
5
F). Next, the wafer periphery is chamfered, and the wafer back surface is flattened as necessary. Next, the high-temperature polysilicon layer on the front surface of the wafer is ground and polished to a thickness of 10-80 &mgr;m, and preferably 20-50 &mgr;m (see FIG.
5
G). Subsequently, a low-temperature amorphous silicon layer or polysilicon layer
17
is formed to a thickness of about 1-5 &mgr;m, and preferably about 2-3 &mgr;m, by low-temperature CVD at about 600° C. (550-700° C.) on the front surface of the wafer, followed by polishing the low-temperature amorphous silicon layer or polysilicon layer
17
for the purpose of mirroring the laminated surfaces.
On the other hand, a silicon wafer
20
to serve as the supporting substrate wafer (which is covered by silicon oxide film
21
here) is prepared (see
FIG. 5H
) The front surface of this wafer is also mirrored. Next, silicon wafer
10
for the above active layer wafer is laminated onto silicon wafer
20
by contacting their respective mirrored surfaces (see FIG.
5
I). Next, heat treatment is performed to increase the lamination strength of the laminated wafer. Next, as shown in
FIG. 5J
, the periphery of this silicon wafer
10
for the active layer is chamfered, and after removing oxide film
21
of silicon wafer
20
for the supporting substrate by washing with HF as necessary, silicon wafer
10
for the active layer is ground and polished.
Furthermore, the amount grounded of this silicon layer
10
for the active layer is the amount at which dielectric isolated oxide film
14
is exposed to the outside, dielectric isolated silicon island
10
A appears on the front surface of high-temperature polysilicon layer
16
partitioned by dielectric isolated oxide film
14
, and adjacent silicon islands are completely separated. A laminated dielectric isolated wafer is produced in this manner.
However, photolithography is employed to form window
12
a
for anisotropic etching of dielectric isolation groove
13
in negative resist film
12
of silicon wafer
10
as previously mentioned.
Photolithography refers to a method for writing a pattern onto the front surface of negative resist film
12
coated onto silicon wafer
10
by exposure to light, followed by development. The following provides an explanation of the flow of the photolithography process while referring to the explanatory drawings of a typical photolithography process of
FIGS. 6A-D
.
To begin with, negative resist
12
is coated onto the front surface of silicon wafer
10
on which is formed mask oxide film
11
(see FIG.
6
A), after which the solvent in negative resist film
12
is effectively removed following coating by pre-baking. Next, negative resist layer
12
is exposed to light, developed and rinsed (see FIG.
6
B). Consequently, window
12
a
for anisotropic etching is formed in negative resist film
12
on the front surface of the wafer. Furthermore, post-baking may be performed after this in which silicon wafer
10
is loaded into a baking oven following this to promote a crosslinking reaction of surface negative resist film
12
and make it harder. Next, negative resist
12
Blum David S
Chaudhari Chandra
Mitsubishi Materials Silicon Corporation
Pillsbury & Winthrop LLP
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