Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-18
2003-07-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S349000, C257S410000, C257S638000, C257S645000, C257S651000
Reexamination Certificate
active
06593615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabrication of semiconductor integrated circuit device structures and, in particular, to a method of filling gaps between narrow metal lines with a carbon-doped, low k dielectric silicon oxide thin film utilizing High Density Plasma-Chemical Vapor Deposition (HDP-CVD), thereby effectively reducing the capacitance between the narrow metal lines.
2. Discussion of Related Art
In the fabrication of semiconductor integrated circuits, several levels of conductive interconnects are typically required to electrically connect the millions of active elements included in the circuit. Insulating materials, such as silicon dioxide (SiO
2
), have been employed to isolate the interconnect wires in a given level of the IC as well as between its different levels. However, as interconnect wiring has become more dense, parasitics due to capacitive coupling negatively impact device performance, thus requiring insulators with lower dielectric constants. Pure SiO
2
thin films have a dielectric constant of around k=4. SiO
2
can be grown by oxidation of pure silicon using O
2
or H
2
O gas, or can be deposited by chemical vapor deposition (CVD) or High Density Plasma-Chemical Vapor Deposition (HDP-CVD) employing reactants such as SiH
4
/Ar/N
2
O, SiH
4
/Ar/NO, and/or SiH
4
/Ar/O
2
gas mixtures as reactants.
Current HDP-CVD SiO
2
processes use SiH
4
and O
2
for deposition along with Ar or He for sputtering. Referring to
FIG. 1A
, conventional CVD SiO
2
processes without a sputtering component result in the formation of voids between adjacent metal lines due to the high sticking probabilities of the precursors SiH
3
and SiH
2
in silane discharges coupled with insignificant surface diffusion. It is known that these voids can be eliminated in deposition of pure SiO
2
films by adding a sputtering component to the HDP-CVD process. Sputtering, which is controlled by applying high frequency bias power to the substrate, bombards the horizontal surfaces of the deposited SiO
2
, as shown in
FIG. 1B
, and pulls back the corners of the gap between structures resulting in complete filling of the gaps between narrowly-spaced metal lines, as shown in FIG.
1
C.
Work has been done wherein SiO
2
has been doped to lower the dielectric constant of the layer. For example, spin coating techniques have been employed to produce carbon-containing SiO
2
spin on glass (SOG) films with dielectric constants approaching k=3.0. While SOG films can be suitable for a great many applications, including providing interconnect dielectrics, they have a number of manufacturing disadvantages. For example, SOG processing involves the use of liquids and produces waste material that requires disposal. Also, SOG processing often produces films that have high OH
−
concentrations. In addition, SOG's often suffer from temperature instability, tensile stress and moisture absorption/desorption problems.
Organically-doped SiO
2
layers have also been deposited using CVD processes. One technique utilizes substitute precursors such as methylsilane (CH
3
—SiH
3
) or phenylsilane (C
6
H
5
/SiH
3
) as a substitute for the SiH
4
precursor. However, with respect to this technique, the methyl group is only partially dissociated and some of the methyl constituents remain bonded to the silicon atom in the oxide layer. The resulting carbon-doped oxide layer has a dielectric constant around k=3. A further technique utilizes CH
3
—SiH
3
and H
2
O
2
as the reactant species.
While attempts have been made in the past to deposit carbon-doped SiO
2
layers utilizing Plasma Enhanced CVD techniques without sputtering, it has been found that the same voids are produced in these processes as those appearing in the deposition of pure SiO
2
layers without sputtering. Past attempts to deposit carbon-doped SiO
2
layers utilizing sputtering have appeared to result in the formation of pure SiO
2
, the sputtering apparently resulting in the carbon species being driven from the SiO
2
structures. Thus, those skilled in the art have been lead away from forming carbon-doped SiO
2
layers using deposition processes enhanced by sputtering.
SUMMARY OF THE INVENTION
The use of carbon containing precursors to replace silane or added to silane and oxygen as the reactant species in an HDP-CVD reactor is desirable to produce a low dielectric constant film.
In accordance with the present invention, we have recognized that allowing substrate bombardment during HDP deposition of a carbon-doped silicon oxide film results in the filling of the intra-metal gaps with low k material having high carbon content. The process leads to the placement of a low k material exactly in the area where it can do the most good. Since the sputter process can only effectively bombard the film on the horizontal surface, the film deposited in the gaps between metal lines is least affected by the bombardment energy and, thus, maintains a carbon content conducive to low k properties. The film deposited over the metal lines has a higher dielectric constant due to the removal of carbon from these upper films during ion bombardment. Thus, the process effectively delivers material in the gap between narrow metal lines that is filled with low k SiOC dielectric which lowers the capacitance between the metal lines. The films over the metal lines have properties similar to SiO
2
and are available for sequential integration processes.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 5821168 (1998-10-01), Jain
patent: 5858869 (1999-01-01), Chen et al.
patent: 5965918 (1999-10-01), Ono
patent: 6030881 (2000-02-01), Papasouliotis et al.
patent: 6184158 (2001-02-01), Shufflebotham et al.
patent: 6444564 (2002-09-01), Raeder
patent: 6448177 (2002-09-01), Morrow et al.
Shu Jen
Thomas Michael E.
Berry Rene′ R.
National Semiconductor Corporation
Nelms David
Stallman & Pollock LLP
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