Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-15
2001-02-27
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S298000, C257S300000, C257S306000, C257S310000, C438S200000, C438S201000, C438S239000, C438S240000, C438S253000, C438S396000, C438S048000
Reexamination Certificate
active
06194752
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a dielectric device having a dielectric film, a dielectric memory using a dielectric film in its gate portion, and a method of fabricating the same.
2. Description of the Related Art
A memory having a capacitor composed of a ferroelectric thin film provided in a gate portion of a field effect transistor (FET) has been known as a nondestructive readable nonvolatile memory. As the structure of such a ferroelectric memory, an MFS (metal-ferroelectrics-semiconductor) structure, an MFIS (metal-ferroelectrics-insulator-semiconductor) structure, an MFMIS (metal-ferroelectrics-metal-insulator-semiconductor) structure, and so forth have been proposed.
In the ferroelectric memory having the MFS structure, a ferroelectric thin film is provided as a gate insulating film of an FET, so that the ferroelectric thin film is brought into direct contact with a semiconductor substrate. Therefore, constituent atoms react with each other and mutually diffuse on the surface of the ferroelectric thin film with the semiconductor substrate. As a result, the characteristics of the ferroelectric memory are degraded, decreasing the reliability thereof.
In the ferroelectric memory having the MFIS structure, an insulating film is provided as a diffusion barrier layer (a buffer layer) for preventing constituent atoms from mutually diffusing between a semiconductor substrate and a ferroelectric thin film. However, the diffusion barrier characteristics of the insulating film are not sufficient, so that the problems of the reaction and the mutual diffusion of the constituent atoms on the surface of the ferroelectric thin film with the semiconductor substrate are not satisfactorily solved.
In the ferroelectric memory having the MFMIS structure, therefore, a capacitor composed of a ferroelectric thin film (hereinafter referred to as a ferroelectric capacitor) is formed on a gate electrode of a normal FET formed on the semiconductor substrate.
FIG. 7
is a schematic cross-sectional view showing one example of the conventional ferroelectric memory having the MFMIS structure.
In
FIG. 7
, a source region
22
composed of an n
+
layer and a drain region
23
composed of an n
+
layer are formed with predetermined spacing on the surface of a P-type silicon substrate
21
. A region of the silicon substrate
21
between the source region
22
and the drain region
23
is a channel region
24
. A gate oxide film
25
, a floating gate electrode
26
, a ferroelectric thin film
27
and a control gate electrode
28
are formed in this order on the channel region
24
.
Description is now made of the principle under which the ferroelectric memory shown in
FIG. 7
operates. A sufficient positive voltage to inversely polarize the ferroelectric thin film
27
is applied to the control gate electrode
28
, to set the voltage of the control gate electrode
28
to zero again. Therefore, the surface of the ferroelectric thin film
27
with the control gate electrode
28
is negatively charged, and the surface of the ferroelectric thin film
27
with the floating gate electrode
26
is positively charged.
In this case, the surface of the floating gate electrode
26
with the ferroelectric thin film
27
is negatively charged, and the surface of the floating gate electrode
26
with the gate oxide film
25
is positively charged, so that an inversion layer is formed in the channel region
24
between the source region
22
and the drain region
23
. As a result, an FET is turned on, although the voltage of the control gate electrode
28
is zero.
Contrary to this, a sufficient negative voltage to inversely polarize the ferroelectric thin film
27
is applied to the control gate electrode
28
, to set the voltage of the control gate electrode
28
to zero again. Therefore, the surface of the ferroelectric thin film
27
with the control gate electrode
28
is positively charged, and the surface of the ferroelectric thin film
27
with the floating gate electrode
26
is negatively charged.
In this case, the surface of the floating gate electrode
26
with the ferroelectric thin film
27
is positively charged, and the surface of the floating gate electrode
26
with the gate oxide film
25
is negatively charged. As a result, no inversion layer is formed in the channel region
24
between the source region
22
and the drain region
23
, so that the FET is turned off.
If the ferroelectric thin film
27
is thus sufficiently polarized inversely, the FET can be selectively turned on or off even after a voltage applied to the control gate electrode
28
is set to zero. Therefore, it is possible to discriminate between data “1” and “0” which are stored in the ferroelectric memory by detecting a current between a source and a drain.
In the ferroelectric memory shown in
FIG. 7
, the ferroelectric thin film
27
is formed on the floating gate electrode
26
composed of a material which is low in reactivity, for example, Pt (platinum), and the gate oxide film
25
and the floating gate electrode
26
function as diffusion barrier layers. Consequently, constituent atoms are prevented from reacting with each other and mutually diffusing between the ferroelectric thin film and the semiconductor substrate, as compared with the ferroelectric memory having the MFS structure and the ferroelectric memory having the MFIS structure.
FIG. 8
is a schematic cross-sectional view showing another example of the conventional ferroelectric memory having the MFMIS structure. The ferroelectric memory shown in
FIG. 8
is disclosed in JP-A-5-327062.
In
FIG. 8
, a source region
34
composed of a p
+
layer and a drain region
35
composed of a p
+
layer are formed with predetermined spacing on the surface of an n
+
silicon substrate
31
. A region of the silicon substrate
31
between the source region
34
and the drain region
35
is a channel region
36
. A gate oxide film
32
is formed on the channel region
36
, and a first lower electrode
33
is formed on the gate oxide film
32
.
An interlayer insulating film
37
is formed on the silicon substrate
31
and the first lower electrode
33
. A contact hole
39
is formed in the interlayer insulating film
37
on the first lower electrode
33
, and a wiring layer
40
is formed in the contact hole
39
.
Contact holes are respectively provided in the interlayer insulating film
37
on the source region
34
and the interlayer insulating film
37
on the drain region
35
, and wiring layers
45
and
46
are respectively formed in the contact holes.
Furthermore, a second lower electrode
42
is formed on the wiring layer
40
connected to the first lower electrode
33
. A ferroelectric thin film
43
is formed on the second lower electrode
42
, and an upper electrode
44
is formed on the ferroelectric thin film
43
. Further, ohmic electrodes
47
and
48
are respectively formed on the wiring layers
45
and
46
which are connected to the source region
34
and the drain region
35
.
In the dielectric memory shown in
FIG. 8
, the ferroelectric thin film
43
is formed on the second lower electrode
42
composed of a material which is low in reactivity, for example, Pt, and the interlayer insulating film
37
is provided between the first lower electrode
33
and the second lower electrode
42
, so that constituent atoms are further prevented from reacting with each other and mutually diffusing between the ferroelectric thin film
43
and the silicon substrate
31
.
In the fabrication of the ferroelectric memory shown in
FIG. 8
, in patterning the upper electrode
44
, the ferroelectric thin film
43
and the second lower electrode
42
by etching, a conductive material such as Pt which is a material for the upper electrode
44
and the second lower electrode
42
which have been etched may, in some cases, adhere or deposit on sidewalls of the ferroelectric thin film
43
. Therefore, a current leaks between the upper electrode
44
and the second lower electrode
42
, so that the
Furukawa Hiroaki
Goto Takashi
Gueshi Tatsuro
Harada Mitsuaki
Ishizuka Yoshiyuki
Armstrong, Westerman Hattori, McLeland & Naughton
Sanyo Electric Co,. Ltd.
Wojciechowicz Edward
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