Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-02-01
2003-12-16
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06664177
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflection coating, DARC, comprised of multiple layers of SiON with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption.
(2) Description of Related Art
As a background to the current invention, it remains a challenge in dual damascene processing to improve the photolithography processing window in a multi-layered dual damascene process by using ARC, anti-reflection coatings, to reduce reflectivity and improve light absorption, to minimized light scattering back from the underlying substrate. One solution is to use a fairly thick layer of SiON as an ARC; but, this method has a significant problem in that the thick SiON film causes defects in a subsequent Ar sputtering process, which in turn leads to yield loss.
The related Prior Art background patents will now be described in this section.
U.S. Pat. No. 6,214,721 entitled “Method and Structure for Suppressing Light Reflections During Photolithography Exposure Steps in Processing Integrated Circuit Structures” granted Apr. 10, 2001 to Bendik, Jr. et al. describes a method for forming dual damascene patterns using a dual ARC, anti-reflection coating process. The dual ARC process incorporates “built-in” wave dampening by having one or more silicon nitride layers remain, as part of a dual damascene “stack” of material layers.
U.S. Pat. No. 6,100,559 entitled “Multipurpose Graded Silicon Oxynitride Cap Layer” granted Aug. 8, 2000 to Park teaches a photolithography process using a graded thin SiON layer, as an anti-reflective coating (ARC) and is graded with varying concentrations of nitrogen.
U.S. Pat. No. 6,060,380 entitled “Anti-reflection Silicon oxynitride Hardmask Layer Used During Etching Processes In Integrated Circuit Fabrication” granted May 9, 2000 to Subramanian et al. describes a method of forming dual damascene trench lines and vias holes using a low reflectivity silicon oxynitride hardmask layer with a photoresist layer over the hardmask layer. After exposure to light, the photoresist layer is patterned more conformally to a desired pattern.
U.S. Pat. No. 6,037,276 entitled “Method for Improving Pattering of a Conductive Layer in an Integrated Circuit” granted Mar. 14, 2000 to Lin et al. discloses a process to pattern a conductive layer using an anti-reflective coating. The process uses a dual cap of oxynitride and silicon nitride, with the oxynitride layer performing as a bottom anti-reflection coating to improve photolithography process performance.
U.S. Pat. No. 5,639,687 entitled “Method for Forming an Integrated Circuit Pattern on a Semiconductor Substrate Using Silicon-Rich Silicon Nitride” granted Jun. 17, 1997 to Roman et al. teaches a photolithography process to pattern an underlying layer using an anti-reflective coating. The process uses a cap layer of silicon-rich silicon nitride which forms an anti-reflection coating over the photoresist, to improve photolithography process performance.
SUMMARY OF THE INVENTION
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of in a multi-layered dual damascene process by using a dielectric anti-reflection coating, DARC, comprised of multiple layers of SiON with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.
Key to the present invention is a multi-layer film scheme for a dielectric anti-reflective coating, DARC, comprised of firstly a bottom layer of silicon oxynitride, SiON, is deposited an intermetal dielectric and the SiON has a dielectric constant k value from approximately 1.0 to 1.4, with the layer thickness from approximately 300 to 500 Angstroms. This bottom layer performs as a light absorption layer to minimize light scattering back from the substrate. Secondly, the multi-layer anti-reflective coating is comprised of a top layer of silicon oxynitride, SiON, deposited over the bottom layer of SiON, and the top SiON has a dielectric constant k value from approximately 0.3 to 0.6, with a layer thickness from approximately 200 to 500 Angstroms. This top layer performs as a phase cancellation layer to destructively interfere with incoming light waves. By the above method, both the reflectivity and the amplitude of the “swing curve” are minimized. Hence, the process window of the dual damascene process is improved.
The advantages of the method of the present invention are at least fourfold:
(a) The top SiON ARC layer performs as a phase cancellation layer to destructively interfere with incoming light waves.
(b) The bottom SiON ARC layer performs as a light absorption layer to minimize light scattering back from the substrate and substrate features, e.g., vias with critical dimensions
(c) The SiON ARC multilayers are made thin and are easily removed by subsequent chem-mech polishing CMP steps in dual damascene processing and do not cause defects in a subsequent critical dimension, via bottom cleaning step by Ar sputter cleaning.
(d) Using relatively thin SiON ARC layers, improves the adhesion of the ARC layers to the intermetal dielectric which is usually an oxide layer. The reduced thickness of the ARC layers lowers the overall intrinsic stress and stress caused by thermal coefficient of expansion mismatch. The thin ARC layers act a “skin” on the intermetal dielectric and are “pinned” to the surface.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.
REFERENCES:
patent: 5639687 (1997-06-01), Roman et al.
patent: 6037276 (2000-03-01), Lin et al.
patent: 6042999 (2000-03-01), Lin et al.
patent: 6060380 (2000-05-01), Subramanian et al.
patent: 6100559 (2000-08-01), Park
patent: 6214721 (2001-04-01), Bendik, Jr. et al.
Lin Kwang-Ming
Liu Kun-Yi
Lu Chung-Hung
Tai Ya-Li
Wu Szu-An
Harrison Monica D.
Taiwan Semiconductor Manufacturing Company
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