Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-29
2001-06-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S628000
Reexamination Certificate
active
06251772
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application contains subject matter related to a concurrently filed U.S. patent application Ser. No. 09/302,036 filed Apr. 29, 1999 now U.S. Pat. No. 6,107,185 by Todd P. Lukanac entitled “Conductive Material Adhesion Enhancement in Damascene Process for Semiconductors”.
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to a manufacturing method for dual damascene semiconductors.
BACKGROUND ART
In the process of manufacturing integrated circuits, after the individual devices such as the transistors have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization” and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is a silicon dioxide or other oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of the first channels. An anisotropic etch, generally an oxide etch, is then used to etch out the channel dielectric layer to form the first channel openings. The damascene step photoresist is then stripped and a conductive material is deposited in the first channel openings.
Some conductive materials, such as copper, require preparatory steps before deposition. An optional adhesion material, such as tantalum or titanium, is deposited followed by a barrier material, such as tantalum nitride or titanium nitride. The combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein. The barrier layer is used to prevent failure causing diffusion of the conductive material of the channels into the dielectric layer and the semiconductor devices. A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent electro-deposition of the conductive material.
The conductive material deposited in the first channel openings and is then subjected to a chemical-mechanical polishing process which removes the materials above the first channel dielectric layer and above the first channel openings. With the chemical-mechanical polishing, the conductive material is “damascened” into the first channel dielectric layer to form the first conductive channels. This chemical-mechanical polishing process attempts to leave the first channel dielectric layer and the conductive material in the channel as smooth and as planar as possible for subsequent operations. This requires the use of a very fine abrasive in the process.
For multiple layers of channels, the “dual damascene” technique is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin dielectric etch stop layer, such as a silicon nitride, over the first channels and the first channel dielectric layer. Subsequently, a via dielectric layer is deposited on the etch stop layer. This is followed by deposition of a thin via dielectric etch stop layer, generally another nitride layer. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A stop layer etch, generally a nitride etch, is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer is then deposited over the via dielectric stop layer and the exposed via dielectric layer. A second damascene step photoresist is placed over the second channel dielectric layer and is photolithographically processed to form the pattern of the second channels. An anisotropic etch is then used to etch the second channel dielectric layer and the via dielectric layer to form the second channel openings and the via areas down to the thin etch stop layer above the first channels. The damascene photoresist is then removed, and a stop layer etch process removes the via etch stop layer above the first channels in the via areas.
For conductive materials such as copper as previously described, a barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to simultaneously fill the second channel and the vias. A second chemical-mechanical polishing process defines the second channel and leaves the two vertically separated channels connected by a cylindrical via. Again, this chemical-mechanical polishing process attempts to leave the first channel dielectric layer and the conductive material in the channel as smooth and as planar as possible for subsequent operations.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
In the past, those skilled in the art tried to make the surfaces resulting from the chemical-mechanical polishing steps as smooth and as planar as possible to provide flat surfaces for subsequent layers and alignment for further photolithographic processing.
With smaller and smaller semiconductor geometries, adhesion of subsequent layers to dielectric materials in semiconductors has been found to be important for reliability. Both chemical and mechanical delamination are sources of semiconductor device failures. Thus, a method for enhancing the adhesion has become increasingly important.
DISCLOSURE OF THE INVENTION
The present invention provides a method for enhancing adhesion to dielectric materials by roughening the surface to increase the surface area for improved chemical and mechanical bonding. After deposition of the conductive material and chemical-mechanical polishing for planarization, the dielectric material is subject to a roughening which will increase the surface roughness by five over the final planarization finish.
The present invention provides a method for improving chemical-mechanical bonding between semiconductor layers by a final coarse polish after chemical-mechanical polishing.
The present invention provides a method for improving chemical-mechanical bonding between semiconductor layers by a high force scrub process after chemical-mechanical polishing.
The present invention provides a method for improving chemical-mechanical bonding between semiconductor layers by a chemical etching process after chemical-mechanical polishing.
The present invention provides a method for improving chemical-mechanical bonding between semiconductor layers by a plasma etching process after chemical-mechanical polishing.
The present invention provides a method for improving chemical-mechanical bonding between semiconductor layers by a high temperature blistering process after chemical-mechanical polishing.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5989623 (1999-11-01), Chen et al.
patent: 6001730 (1999-10-01), Farkas et al.
patent: 6010962 (2000-01-01), Liu et al.
patent: 6048796 (2000-04-01), Wang et al.
Advanced Micro Devicees, Inc.
Ishimaru Mikio
Le Dung A
Nelms David
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