Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2002-06-17
2003-07-01
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S737000, C257S738000, C257S784000, C257S786000, C257S675000, C257S787000, C257S734000, C257S717000, C257S684000
Reexamination Certificate
active
06586834
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to integrated circuit packaging, and more particularly to a method of manufacture of a tape ball grid array package with improved thermal and electrical performance.
BACKGROUND OF THE INVENTION
High performance integrated circuit (IC) packages are well known in the art. Improvements in IC packages are driven by demands for increased thermal and electrical performance, decreased size and cost of manufacture.
In general, array packaging such as Plastic-Ball Grid Array packages provide a high density of interconnects relative to the surface area of the package. However typical PBGA packages include a convoluted signal path, giving rise to high impedences and an inefficient thermal path which results in low thermal dissipation performance.
Typically, array packaging such as ball grid array (BGA) packages provide for a high density package. Applicants' prior Tape Ball Grid Array (TBGA) product is an advanced IC package having straight signal paths and a copper backed, die down construction which enjoys enhanced performance over prior art PBGA packages. There are still further demands, for increased thermal and electrical performance, however.
It is an object of an aspect of the present invention to provide a method for manufacturing an IC package with improved thermal and electrical performance as well as the opportunity for a full array of interconnect balls at the backside of the package not found in a typical die down format.
SUMMARY OF THE INVENTION
In a particular aspect, the IC package of the present invention includes a flexible circuit tape. The flexible circuit tape has a flexible tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and the conductor layer. A copper leadframe is fixed to the flexible circuit tape and electrically isolated from the conductor layer. The copper leadframe has a die attach pad and heat spreader portions, the through holes in the flexible circuit tape extending through to the copper leadframe. A semiconductor die is mounted on the die attach pad. Wire bonds extend from pads on the semiconductor die to the die attach pad and from other pads on the semiconductor die to the conductor layer. An encapsulating material encapsulates the semiconductor die and the wire bonds.
In another aspect of the present invention, the IC package includes a flexible circuit tape. The flexible circuit tape has a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and the conductor layer. A copper leadframe is fixed to the flexible circuit tape and electrically isolated from the conductor layer. The copper leadframe includes an etched down die attach pad and heat spreader portions. The die attach pad is etched down such that at least a portion of the die attach pad is reduced in thickness. The through holes in the flexible circuit tape extend through to the copper leadframe. A semiconductor die is mounted on the at least a portion of the die attach pad. Wire bonds extend from pads on the semiconductor die to the die attach pad and from other pads on the semiconductor die to the conductor layer. An encapsulating material encapsulates the semiconductor die and the wire bonds. A plurality of solder ball contacts in the through holes are fixed to the copper leadframe and a plurality of solder ball contacts in the blind holes are fixed to the conductor layer.
In another aspect of the present invention, the IC package is manufactured by: providing a flexible circuit tape having a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and the conductor layer; fixing a copper leadframe to the flexible circuit tape and electrically isolating the copper leadframe from the conductor layer, the copper leadframe including an etched down die attach pad and heat spreader portions, the die attach pad being etched down such that at least a portion of the die attach pad is reduced in thickness, the through holes in the flexible circuit tape extending through to the copper leadframe; mounting a semiconductor die on the at least a portion of the die attach pad; wire bonding from pads on the semiconductor die to the die attach pad and from other pads on the semiconductor die to the conductor layer; encapsulating the semiconductor die and the wire bonds; fixing a plurality of solder ball contacts in the through holes, to the copper leadframe; and fixing a plurality of solder ball contacts in the blind holes, to the conductor.
In one aspect of the present invention, solder balls are directly soldered to portions of the leadframe. Advantageously, the solder balls have a low impedance on ground. Further, this provides an extra thermal path from the leadframe to the motherboard, for thermal dissipation. Also, it is an advantage of an aspect of the present invention that the semiconductor die sits in a portion of the die attach pad that is reduced in thickness and therefore the length of the wire bonds (both to the die attach pad (ground bonds) and to the bond fingers (I/O bonds) can be reduced. Because electrical impedance in an IC package is directly related to the wire length, this construction allows for a package suitable to operate at higher frequencies.
A further advantage of an aspect of the present invention is provided by the three dimensional nature of the partial etch die attach pad. This pad provides additional exposed metal for the mold compound to adhere to, thereby providing a more robust package.
Still further, it is an advantage of an aspect of the present invention that the die and wire bonds are lower in the profile of the package. This allows the option of reducing the package profile.
REFERENCES:
patent: 6011694 (2000-01-01), Hirakawa
patent: 6140707 (2000-10-01), Plepys et al.
patent: 6153924 (2000-11-01), Kinsman
patent: 6246111 (2001-06-01), Huang et al.
Lam Wing Keung
Sze Ming Wang
Tsang Kwok Cheung
Wong Kin-wai
Asat Ltd.
Keating & Bennett LLP
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