Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-01-18
2003-07-08
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06590225
ABSTRACT:
PRIOR ART DESCRIPTION
FIG. 1
illustrates a semiconductor wafer
101
comprising multiple die
102
. After the wafer
101
is manufactured all die
102
on the wafer must be tested to identify good die from bad die. The testing of all die on wafer can be a time consuming process, especially when the die contain multiple complex digital and/or analog circuits, which is the current trend in the semiconductor industry.
FIG. 2
illustrates a more detail example of one of the die
102
. As seen in
FIG. 2
, the die
102
contains multiple embedded circuits A-I. The circuits A-I could be any type of circuits such as digital signal processor cores, microprocessor cores, mixed signal circuits such ADCs and DACs, peripherals, or memories. Each circuit A-I has input
201
and output
202
terminals. The die has input
203
and output
204
pads for connecting to external circuitry. Internally, the circuits A-I are connected together at their input
201
and output
202
terminals via connections
206
, allowing them to function together. Certain of the circuits A-I are connected to the die input
203
and output
204
pads via connections
205
and
207
to allow external communication. Typically, during the test of the die
102
, each circuit A-I is individually tested. The following examples in
FIGS. 3 and 4
describe how a conventional test approach can be used for selecting and testing the circuits A-I of die
102
.
FIG. 3
illustrates a prior art test approach whereby the die is configured to connect the input
201
and output
202
terminals of circuit E to the die input
203
and output
204
pads via test bussing paths
301
-
304
. A similar test approach where inputs and outputs of embedded circuits are bussed to die pads for testing, as shown in
FIG. 3
, is described in TI U.S. Pat. No. 5,005,173.
FIG. 4
illustrates an example test arrangement
400
consisting of die
102
to be tested, tester
401
to supply test patterns, and probe mechanism
402
for making connections between tester
401
and pads of die
102
. It is assumed that Die
102
is configured for testing circuit E as described in regard to FIG.
3
. During test, the tester
401
outputs test stimulus patterns to the input terminals
201
of circuit E via input pads
203
and test bussing paths
301
and
302
, and inputs test response patterns from output terminals
202
of circuit E via test bussing paths
303
and
304
. In this example, it is assumed that circuit E does not contain design for test features, such as scan design, so functional testing must be performed on circuit E by manipulation of all, or at least a significant number of, the circuit E input and output terminals.
When testing of circuit E is complete, another circuit, such as D may be selected and connected to the input
203
and output
204
pads, via additional test bussing paths, like
301
-
304
, and tested like circuit E was described being tested. During the testing of die
102
, all circuits A-I will eventually be selected and tested in the manner described above. Since some of the circuits A-I are directly connected on at least some of their input
201
and output
202
terminals to input
203
and output
204
pads, fewer additional test bussing paths may be required for their testing. However, all circuits A-I that have input
201
and output
202
terminals that are not functionally connected to input
203
and output
204
pads will require a test bussing path to be configured during test.
While the test approach of using configurable test bussing paths to select and test embedded circuits, as described above, is a simple process, it introduces two key problems. The first problem is that the additional test bussing paths required for selecting and testing the circuits adds circuitry and wiring overhead to the die, thus increasing die size and potentially increasing the amount of noise and crosstalk produced during functional operation of the die. The second problem is that when some of the input
203
and output
204
pads are being used to test one of the circuits A-I, they cannot necessarily also be used to test another of the circuits A-I. For example, since some of the input
201
terminals of circuits D and E are connected during test to a common set of input
203
pads, via test bus
301
, it is not possible to test circuits D and E simultaneously. Thus, testing of the circuits A-I of die
102
may need to occur in a one-at-a-time fashion, which leads to longer die test times. The present invention, as described in detail below, provides solutions for these two problems.
REFERENCES:
patent: 5506499 (1996-04-01), Puar
patent: 5594273 (1997-01-01), Dasse et al.
patent: 5642057 (1997-06-01), Oke et al.
patent: 5799021 (1998-08-01), Gheewala
patent: 5838023 (1998-11-01), Goel et al.
patent: 5949090 (1999-09-01), Iwasa et al.
patent: 6169418 (2001-01-01), Wagner
Antley Richard L.
Whetsel Lee D.
Bassuk Lawrence J.
Brady W. James
Smoot Stephen W.
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