Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2001-08-07
2002-08-20
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S691000
Reexamination Certificate
active
06437431
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a power distribution system for routing external power across a die.
BACKGROUND OF THE INVENTION
Integrated circuits are typically packaged before they are used with other components as part of a larger electronic system. Wire-bond ball grid array (BGA) packages are constructed with die mounted on a substrate with bond pads on the die connected to conductive lines or traces on the surface substrate. One area of concern for wire bond-BGA packages is power distribution to the die.
FIG. 1
is a top view of a conventional power mesh on a die for redistributing external power across the die. A conventional power mesh
10
typically comprises a series of power pads
12
evenly distributed around the periphery of the die
14
, and at least two power redistribution layers of vertical and horizontal metal interconnects called power lines
16
and
18
. The purpose of the power mesh
10
is to redistribute external power from the power pads
12
located around periphery of the die
14
to the center of the die
14
.
The two power redistribution layers are referred to as the top redistribution layer (R) and the lower redistribution layer (R-
1
). Each redistribution layer includes two types of power lines
16
and
18
, VDD for power and VSS for ground.
The R layer comprises a series of relatively thick power lines
16
that run either horizontally or vertically, where each connects a pair of power pads
12
located on opposite sides of the die
14
.
FIG. 1
, for instance, shows the power lines
16
of the top R layer patterned vertically across the die
14
to connect power pads
12
located on the top and bottom sides of the die
14
.
The R-
1
layer below the R layer comprises a series of relatively thin power lines
18
(2.5x to 10x thinner than the R layer) that run perpendicular to the R layer to connect the power pads
12
located on the opposite two sides of the die
14
.
Although the power redistribution layers effectively route power across the die
14
, the current power distribution methodology fails to evenly distribute power across the power mesh
10
. More specifically, the interior of the die
14
may experience a voltage drop due to the length of the power lines
16
and
18
. For example, assuming that the external power source is 5 V, then the die
14
may experience a 5 V-10% drop at the center.
A related problem is that the power flow from the core of the die
14
to the power supply is not evenly distributed across all available power pads
12
. The wide R layer has little resistance and therefore carries more current, while the thinner R-1 layer has a higher resistance and therefore carries less current. This may result in electromigration issues for the power pads
12
connected to the R layer, since they tend to drive more current than the power pads
12
connected on the R-
1
layer. Trying to resolve the electromigration issue by adding more pads on the sides connected by the R layer will also result into an asymmetry of the distribution of the pads. For example the sides connected by the R layer may have far less signal pads than the side connected by the R-
1
layer, just because most of the VDD/NSS pads will be on side supported by the R-layer.
A third problem with the current power distribution methodology is that the power mesh
10
requires at least two metal layers, R and R-
1
. Unfortunately, the R-
1
layer is a routing resource that could be used for signal routing rather than power routing, which could result in smaller die
14
sizes.
Accordingly, what is needed is an approved power mesh that achieves symmetry in power distribution both within the die and through the power pads. The power pads should also be evenly distributed along the chip sides. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a system and method for distributing external power across a die. The die has multiple sides and a plurality of power bond pads located along each of the sides for receiving an external power signal. The system and method include patterning a plurality of straight power lines that form a single-layer power mesh diagonally across the die to connect power the bond pads that are located on two different sides of the die. As an alternative to the first embodiment, the diagonal power lines are patterned in a stair-step configuration for ease of manufacturing.
According to the method system disclosed herein, because the power lines are routed diagonally across the die, all the power bond pads can be connected without the need for a second layer, thereby providing a single-layer power mesh. The single-layer power mesh of the present invention achieves symmetry in power distribution both within the die and an even distribution of current flow through the power pads. In addition, the single-layer power mesh frees a routing resource for signal routing, and this results into a significant die size decrease.
REFERENCES:
patent: 5719449 (1998-02-01), Strauss
patent: 6344976 (2002-02-01), Schoenfeld et al.
Mbouombouo Benjamin
Sabada Sudhakar
Jr. Carl Whitehead
LSI Logic Corporation
Rose Kiesha
Sawyer Law Group LLP
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