Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2006-08-29
2006-08-29
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S088000, C257S100000, C257S737000, C257S780000
Reexamination Certificate
active
07098518
ABSTRACT:
In one embodiment of the invention, a die-level opto-electronic device comprises a semiconductor die having edges and a photonic device exposed on a first surface. The device includes a conductive structure formed in the die and away from the edges of the die, the conductive structure being exposed on a second surface of the die that opposes the first surface, wherein the conductive structure is electrically connected to the photonic device. The device also includes an optically transparent laminate attached to the first surface so as to overlay the photonic device.In another embodiment of the invention, a semiconductor wafer comprises a substrate having a plurality of photonic devices exposed on a first surface. A plurality of conductive structures is formed in the substrate, the plurality of structures being exposed on a second surface of the substrate that opposes the first surface, wherein ones of the plurality of structures are electrically connected to associated ones of the plurality of photonic devices. An optically transparent laminate is attached to the first surface so as to overlay the plurality of photonic devices.Methods of forming the die-level opto-electronic devices and semiconductor wafers of the invention are also described.
REFERENCES:
patent: 5621225 (1997-04-01), Shieh et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6498381 (2002-12-01), Halahan et al.
patent: 6607941 (2003-08-01), Prabhu et al.
patent: 6677235 (2004-01-01), Yegnashankaran et al.
patent: 6703689 (2004-03-01), Wada
patent: 6730459 (2004-05-01), Nishikawa et al.
patent: 6759687 (2004-07-01), Miller et al.
patent: 2003/0193078 (2003-10-01), Chungpaiboonpatana et al.
patent: 2003/0230805 (2003-12-01), Noma et al.
Reche, John, “Wafer Thinning and Thru-Silicon Vias: The Path to Wafer Level Packaging”, Tru-Si Technologies, IEEE/CPMT Meeting, Santa Clara, CA, May 10, 2000, 42 Pages.
Tru-Si Technologies, “Thru Silicon Interconnects”, 33 Pages.
Advanced Semiconductor Engineering Korea, Inc., “CMOS Image Sensor”, http://www.asekr.com/doc/ASE—korea—Image—Sensor—overview.pdf, pp. 4 and 5.
Mostafazadeh Shahram
Smith Joseph O.
Beyer Weaver & Thomas LLP
National Semiconductor Corporation
Parekh Nitin
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