Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2001-09-17
2004-08-31
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S788000, C257S789000, C257S791000, C257S792000, C257S795000, C438S118000, C156S329000, C156S922000
Reexamination Certificate
active
06784555
ABSTRACT:
The invention disclosed herein deals with die attach adhesives and methods for their use, along with the devices that are obtained by the use of the methods.
Using semiconductor chips as an example, the adhesives and the method for using them provides an interface between a chip (die) and the chip support. The method includes creating a space between the chip and the chip support of a given sized opening.
BACKGROUND OF THE INVENTION
In the construction of semiconductor assemblies, it has been found that curable elastomeric materials can be used to create a space between the semiconductor and its support, such construction being disclosed in the U.S. patents of the prior art discussed infra. The most common is the assembly of one or more semiconductor chips on a substrate such as polyimide film which forms part of a chip carrier package including a circuit panel or chip housing.
A chip carrier includes a dielectric layer with an array of terminals and may also contain leads. The chip carrier is fastened to a semiconductor chip through the leads or wire bonds. An elastomeric material is disposed between the chip and the flexible dielectric layer of the chip carrier. The chip carrier and elastomeric material are also referred to as an “interposer” or “interposer layer”, by those skilled in the art. The leads or wire bonds of the chip carrier are bonded to the chip so that the terminals of the carrier are electrically connected to the contacts on the chip. The entire structure can then be mounted to a substrate such as a circuit panel or chip housing. The terminals of the chip carrier are electrically connected to contacts on the substrate. The elastomeric layer provides resiliency to the individual terminals allowing each terminal to move as necessary to accommodate tolerances during testing and in the final assembly itself.
PRIOR ART
The details of the information set forth just above can be found in U.S. Pat. No. 5,477,611 which issued on Dec. 26, 1995 to Sweis, et al, which describes the manufacture of a chip device.
U.S. Pat. No. 5,148,266 which issued on Sep. 15, 1992 to Khandros, et al; U.S. Pat. No. 5,346,861 which issued on Sep. 13, 1994 to Khandros, et al, and U.S. Pat. No. 5,347,159 which issued on Sep. 13, 1994 to Khandros, et al, are based on the same essential disclosure and are also relevant for showing the component parts of chip assemblies and their current manufacturing processes. U.S. Pat. No. 5,477,611 shows the use of liquid resins to create a gap between the chip and the substrate. This material is injected as a liquid and then hardened (cured). The disclosure shows that the material, as it reaches the edges of the chip configuration, creates a meniscus along all outside edges, that are exposed to the atmosphere, which meniscus cures prior to the final cure of the interposed layer. This “B-staging” of the edge through the meniscus creates an in-situ mold that contains the liquid between the chip and the substrate until the final cure takes place.
Except for the disclosure of the use of a curable liquid as an interposer material, there is nothing in the above-mentioned patents about creating a gap between the chip and a substrate as provided by the instant invention.
With regard to the prior art dealing with the use of particulate materials as spacers creating the gap between the chip and the substrate, one should be aware of Japanese patent application number H11-193828, filed Jul. 8, 1999 in the name of Isshiki, et al, wherein there is disclosed the use of a die attach adhesive that is based on a curable polymer composition containing a spherical filler with an average particle diameter of from 100 to 1,000 &mgr;m and a major axis to minor axis ratio of from 1.0 to 1.5. What is disclosed and emphasized therein is the use of certain size particles of inorganic spherical fillers as spacers in the composition.
Likewise, Japanese patent application H11-193829, filed Jul. 8, 1999 in the name of Yamaka, et al, deals with die attach adhesives for bonding semiconductor chips to chip mounting components wherein the adhesive comprises a curable polymer composition containing a spherical filler as spacer particles with an average particle diameter of from 10 to 100 &mgr;m and a major axis to minor axis ratio of 1.0 to 1.5, and they are used in an amount in the range of about 1 to 900 ppm in those formulations.
Finally, Japanese Laid-Open Patent Application (Kokai) No. 7-292343 discloses an adhesive agent for a semiconductor device which is comprised of (A) an organo-polysiloxane having at least two silicon atom bonded alkenyl groups per molecule, (B) an organopolysiloxane having at least two silicon atom bonded hydrogen atoms per molecule, (C) an organosilicon compound having a silicon atom bonded alkoxy group, (D) an organic or inorganic spherical filler whose particle diameter is 10 to 100 &mgr;m and whose major and minor diameter ratio is 1.0 to 1.5, and (E) a catalytic amount of platinum or a platinum compound.
None of the above-identified references recognized the critical parameters set forth for this invention for a successful die attach adhesive based on inorganic insulating particles as spacer beads.
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Chambliss Alonzo
Dow Corning Corporation
McKeller Robert L.
LandOfFree
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