Diagonal matrix delay

Details Diagonal matrix delay Diagonal matrix delay

2006-05-23

2006-05-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050

Reexamination Certificate

active

07050341

ABSTRACT:
A diagonal matrix delay includes a plurality of rows of first buffers in serial communication with an input signal. The diagonal matrix delay includes a plurality of second buffers. Each second buffer is responsive to an output of an associated first buffer and to a column selection signal. The diagonal matrix delay includes a plurality of control lines. Each control line supplies column selection signals to the corresponding second buffers associated with each of the plurality of rows. Corresponding second buffers controlled by a control line are offset between contiguous rows by at least one column to form a substantially diagonal arrangement of columns of second buffers relative to the plurality of rows of first buffers.

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