Diagnostic scheme for programmable logic in a system on a chip

Details Diagnostic scheme for programmable logic in a system on a chip Diagnostic scheme for programmable logic in a system on a chip

2006-01-10

2006-01-10

Myers, Paul R. (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C714S030000, C714S024000

Reexamination Certificate

active

06985980

ABSTRACT:
A scheme for freezing the clock of a CSOC to obtain a static view of the hardware for debugging purposes. A breakpoint unit is programmed to break on specific conditions or sequence of events. The breakpoint unit monitors the bus. Upon the occurrence of the programmed event the breakpoint unit generates a clock freeze signal. The clock freeze event signal is input to the bus arbiter which causes the bus arbiter to stop granting access to the bus to any bus master except the debug port. The bus arbiter checks for pending transactions on the bus and monitors the completion of any pending transactions. This ensures that the system will not be frozen while in a wait state which would render the bus inoperable. Once all pending transactions are complete, the bus arbiter generates a qualified clock freeze signal to the CSL clock thereby freezing the system for debugging.

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