Diagnostic memory interface test

Details Diagnostic memory interface test Diagnostic memory interface test

2006-06-13

2006-06-13

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S738000

Reexamination Certificate

active

07062678

ABSTRACT:
Disclosed is a test method for a computer microprocessor adapted to stress the data transfer interfaces within a microprocessor. The method incorporates patterns designed to stress the interfaces and are further repeated in different widths such that interfaces of various bus widths are fully stressed. Further, the method begins with the various test patterns preloaded into memory to maximize the speed and thus the stress of the test.

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