Diagnostic architecture using FPGA core in system on a chip...

Details Diagnostic architecture using FPGA core in system on a chip... Diagnostic architecture using FPGA core in system on a chip...

2000-10-06

2004-12-07

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06829751

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for a Field Programmable Gate Array (FPGA) core generally and, more particularly, to a diagnostic method and/or architecture using an FPGA core in a system on a chip (SOC) design.
BACKGROUND OF THE INVENTION
A number of conventional approaches to chip design include (i) directly connecting internal signals to chip I/O pins using multiple layers of multiplexers; (ii) reading on-chip readable registers through host interfaces; (iii) running resistor-transistor logic (RTL) simulations to create special cases to find bugs and verify a fixed solution; and (iv) using emulators to verify the design.
The first conventional approach is limited by the number of the chip I/O pins that can be used to access the internal signals. For example, with 2 layers of 8 to 1 multiplexers, up to 8 signals are needed to be probed simultaneously, totaling 3+3+8=14 I/O pins that are needed for the design. With chip gate counts over 1 million gates, good coverage is difficult to achieve with such an approach.
The second conventional approach can only capture a snap shot of the on-chip readable registers. While such an approach can be helpful in identifying the existence of a bug, it does not offer enough information to precisely locate the bug. Additionally, special effort is needed in the design phase to organize all of the registers.
The third conventional approach can access all the chip internal signals, but has drawbacks. First, such an approach is a software simulation approach that is very time consuming. The simulation speed is usually thousands of times slower than the real system. Second, since such an approach is a software simulation method, it cannot reflect all the factors in the real system. Third, some bugs may not be uncovered with the RTL simulation method because of the running time limitation or the difficulty in creating the simulation case.
The fourth conventional approach can run at a speed up to 1 MHz. However, the emulator is very expensive (i.e., about $1 per gate). Implementing such an emulator is not easily accomplished. Additionally, the verification cost can be very high.
Therefore, it would be desirable to provide a system for chip design that would minimize the drawbacks associated with conventional systems.
SUMMARY OF THE INVENTION
The present invention concerns a system for designing an integrated circuit (IC) . The system generally comprising a circuit and a programmable portion used for diagnostics and finding bugs. The circuit generally comprises (i) a functional portion and (ii) a logic portion that may be connected to the functional portion. The logic portion generally includes one or more interfaces. The programmable portion may be configured to detect, correct and/or diagnose errors in the logic portion through the one or more interfaces.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a diagnostic architecture using an FPGA core in a system on-chip design that may (i) ease bringing up, verification and debugging by providing interconnection and programming options; (ii) observe important signals while the chip is running under a normal mode; (iii) run at a single step mode while under the control of the FPGA core; (iv) display appropriate signals on a debugging workstation, allowing many debugging features to be supported such as: (a) triggering and tracing based on internal signals, (b) dynamically changing host register values and (c) providing complex monitoring functions, since the FPGA is programmed; (v) reduce debugging/verification time and/or (vi) improve product time to market.


REFERENCES:
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patent: 6134676 (2000-10-01), VanHuben et al.
patent: 6434735 (2002-08-01), Watkins
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6477683 (2002-11-01), Killian et al.

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