Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-01-02
2004-11-30
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S048000, C713S002000
Reexamination Certificate
active
06826713
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates generally to debugging and diagnostic systems and, more particularly, to systems that exchange diagnostic information with multiple processors in a complex electrical system.
B. Description of Related Art
Conventional networks typically include routers that route packets from one or more sources to one or more destinations. A packet is a variable size record that is transmitted through a network. A router is a network device that receives packets containing data and control information at input ports, and, based on destination or other information included in the packets, routes the packets to appropriate output ports that lead to either the next router in the packet's journey or to the packet's final destination. Routers determine the proper output port for a particular packet by evaluating header information included in the packet.
Routers, particularly high-performance routers, can be complex devices that include multiple processors and other circuitry integrated into a single physical box. For example, a router may include physical interface cards (PICs), modules for holding the physical interface cards (sometimes called flexible PIC concentrators), a routing engine, and switching and forwarding modules. Each one of these components may be implemented on a separate circuit board controlled by one or more processors. These circuit boards may then be mounted in a single physical frame to form the router.
Any of the multiple processors that control the circuit boards in the router may malfunction. Accordingly, it is desirable that the processors execute instructions that allow a designer to receive diagnostic or debugging information so that the designer can pinpoint and correct the problem. Conventionally, such processors included some type of high-level diagnostic ability, such as allowing a telnet session through an Ethernet port. Although such high-level diagnostic procedures can be useful, they are not helpful if the malfunction renders the high-level diagnostic protocol inoperative.
A further potential problem with conventional diagnostic protocols is that each processor may have a separate port that the user must physically connect a cable to in order to view the diagnostic information for that processor. Wiring each processor separately can require a lot of cable and can be inconvenient and awkward for the user, particularly in systems with a large number of processors, any of which can be difficult to access when physically secured in the complete system.
Accordingly, there is a need in the art to improve access to processor diagnostic information in complex multi-processor systems.
SUMMARY OF THE INVENTION
Systems and methods consistent with the present invention address this and other needs through a low-level debugging and diagnostic system implemented in a complex electrical system.
One aspect of the present invention is directed to a system comprising a number of processors implemented on circuit boards and a number of receiver/driver circuits each connected to a serial port of one of the plurality of processors. Additionally, a master processor is coupled to the receiver/driver circuits to select one of the plurality of processors as an active processor for communicating diagnostic information. to the master processor.
A second aspect of the present invention is directed to a method of obtaining diagnostic information from at least one of a number of processors in an electrical system. The method comprises receiving a request to receive diagnostic information from one of the processors and connecting the selected processor to a bus. Further, the non-selected processors are electrically insulated while the diagnostic information from the selected processor is received via a serial communication session transmitted over the bus. The selected processor is brought on-line by executing boot code, the boot code causing the selected processor to transmit the diagnostic information before the boot code is fully loaded.
A third aspect of the present invention is directed to a network device including a bus, a packet forwarding engine, and a routing engine. The packet forwarding engine has a plurality of circuit boards each including at least one processor and a receiver/driver circuit associated with each of the processors. The routing engine is connected to the bus and includes a master processor, the master processor selects one of the processors as an active processor for communicating diagnostic information by instructing the receiver/driver circuit associated with the selected processor to logically connect the selected processor to the bus.
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Microsoft Press Computer Dictionary, 1997, Microsoft Press, Third Edition, p. 376.*
Microsoft Press Computer Dictionary, 1997, Microsoft Press, Third Edition.
Beesley Michael
Heitkamp Ross
Krishnamurthi Ashok
Powell Kenneth Richard
Beausoliel Robert
Harrity & Snyder LLP
Juniper Networks, Inc.
Maskulinski Michael
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