Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-03-29
2011-03-29
Landau, Matthew C (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000, C257SE21014, C257SE29264
Reexamination Certificate
active
07915659
ABSTRACT:
A method that includes forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity. System and devices are also provided.
REFERENCES:
patent: 3885861 (1975-05-01), Farnsworth et al.
patent: 5160987 (1992-11-01), Pricer et al.
patent: 5196910 (1993-03-01), Moriuchi et al.
patent: 5661061 (1997-08-01), Usuami et al.
patent: 5821513 (1998-10-01), O'Hagan et al.
patent: 5858829 (1999-01-01), Chen
patent: 5925918 (1999-07-01), Wu et al.
patent: 5949057 (1999-09-01), Feng
patent: 6008513 (1999-12-01), Chen
patent: 6043562 (2000-03-01), Keeth
patent: 6081008 (2000-06-01), Rostoker
patent: 6100129 (2000-08-01), Tu et al.
patent: 6130551 (2000-10-01), Agrawal et al.
patent: 6216257 (2001-04-01), Agrawal et al.
patent: 6258656 (2001-07-01), Lange et al.
patent: 6258659 (2001-07-01), Gruening et al.
patent: 6268243 (2001-07-01), Park
patent: 6282113 (2001-08-01), DeBrosse
patent: 6316309 (2001-11-01), Holmes et al.
patent: 6380759 (2002-04-01), Agrawal et al.
patent: 6391753 (2002-05-01), Yu
patent: 6432769 (2002-08-01), Fukuda et al.
patent: 6440792 (2002-08-01), Shaio et al.
patent: 6605514 (2003-08-01), Tabery et al.
patent: 6649979 (2003-11-01), Jang
patent: 6689660 (2004-02-01), Noble et al.
patent: 6845033 (2005-01-01), Kirihata et al.
patent: 6897107 (2005-05-01), Divakaruni et al.
patent: 6927462 (2005-08-01), Goodwin et al.
patent: 6967147 (2005-11-01), Tews et al.
patent: 6998666 (2006-02-01), Beintner et al.
patent: 7091543 (2006-08-01), Tzeng et al.
patent: 7098105 (2006-08-01), Juengling
patent: 7099216 (2006-08-01), Luk et al.
patent: 7132333 (2006-11-01), Schloesser et al.
patent: 7151023 (2006-12-01), Nayfeh et al.
patent: 7190060 (2007-03-01), Chiang
patent: 7195995 (2007-03-01), Mouli
patent: 7205606 (2007-04-01), Tran
patent: 7345937 (2008-03-01), Yoon et al.
patent: 7452766 (2008-11-01), Aritome
patent: 7601583 (2009-10-01), Jang et al.
patent: 2001/0003034 (2001-06-01), Furukawa et al.
patent: 2002/0155656 (2002-10-01), Hayano et al.
patent: 2003/0168676 (2003-09-01), Itabashi et al.
patent: 2003/0198073 (2003-10-01), Keeth
patent: 2004/0016953 (2004-01-01), Lindsay et al.
patent: 2004/0027848 (2004-02-01), Wald et al.
patent: 2004/0043592 (2004-03-01), Goodwin et al.
patent: 2004/0062069 (2004-04-01), Keeth
patent: 2004/0125636 (2004-07-01), Kurjanowicz et al.
patent: 2004/0202027 (2004-10-01), Kuzmenka et al.
patent: 2005/0133852 (2005-06-01), Shau
patent: 2005/0151206 (2005-07-01), von Schwerin
patent: 2005/0196918 (2005-09-01), von Schwerin
patent: 2005/0245024 (2005-11-01), von Schwerin
patent: 2006/0006446 (2006-01-01), von Schwerin
patent: 2006/0046407 (2006-03-01), Juengling
patent: 2006/0057814 (2006-03-01), Weis
patent: 2006/0073662 (2006-04-01), Jang et al.
patent: 2006/0076602 (2006-04-01), Harter et al.
patent: 2006/0131651 (2006-06-01), Sato et al.
patent: 2006/0244106 (2006-11-01), Morikado
patent: 2006/0246607 (2006-11-01), Fazan et al.
patent: 2006/0270151 (2006-11-01), Lee
patent: 2006/0273415 (2006-12-01), Kim
patent: 2006/0281250 (2006-12-01), Schloesser
patent: 2007/0010058 (2007-01-01), Juengling
patent: 2007/0023805 (2007-02-01), Wells et al.
patent: 2007/0052040 (2007-03-01), von Schwerin
patent: 2007/0090443 (2007-04-01), Choi et al.
patent: 2007/0111455 (2007-05-01), Kim et al.
patent: 2007/0121414 (2007-05-01), Butler
patent: 2007/0134878 (2007-06-01), Brask et al.
patent: 2007/0145450 (2007-06-01), Wang et al.
patent: 2007/0166933 (2007-07-01), Song et al.
patent: 2007/0170522 (2007-07-01), Lee et al.
patent: 2007/0176221 (2007-08-01), Nakamura
patent: 2007/0176222 (2007-08-01), Ikemasu et al.
patent: 2007/0176253 (2007-08-01), Wang et al.
patent: 2007/0190736 (2007-08-01), Liu et al.
patent: 2007/0262375 (2007-11-01), Juengling
patent: 19946719 (2001-04-01), None
patent: 2006054431 (2006-02-01), None
patent: 930005234 (1993-06-01), None
patent: 20020018071 (2002-03-01), None
patent: 380316 (2000-01-01), None
patent: 388125 (2000-04-01), None
patent: WO 9728532 (1997-08-01), None
patent: WO 0161738 (2001-08-01), None
patent: WO 0231878 (2002-04-01), None
patent: WO 0249100 (2002-06-01), None
patent: WO 2004/038770 (2004-05-01), None
Betty Prince, Ph.D.; “Trends in Scaled and Nanotechnology Memories”; Memory Strategies International; Leander, Texas; 2005.
Branislav Curanovic; “Development of a Fully-Depleted Thin-Body FinFET Process”; Department of Microelectronic Engineering, College of Engineering; Rochester Institute of Technology; Rochest, New York; Nov. 2003.
Claeys, Cor; “Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects”; Proceedings of the 17th International Conference on VLSI Design (VLSID '04); 1063-9667/04; IEEE Computer Society; Leuven Belgium.
Enrico Gili; “Fabrication of Vertical MOSFETs With Reduced Parasitics and Suppression of Short Channel Effects”; Department of Electronics and Compter Science, Microelectronics Group; University of Southampton, Jun. 2004 http://66.102.1.104/scholar?hl=en&lr=&q=cache:BErKI49qg2MJ:www.ecs.soton.ac.uk/˜eg02r/Publications/MinithesisEGili.pdf+dram+fins+%22process+flow%22+%22vertical+access%22.
F. Fishburn, et al.; “A 78nm 6F2 DRAM Technology for Multigigabit Densities”.
J. Sturm, et al.; “Increased Transconductance in Fully-Depleted Ultra-Thin Sillicon-on-Insulator MOSFETs”; 6 pages.
R. Katsumata, et al.; “Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM”; 2003 Symposium on VLSI Technology Digest of Technical Papers; Jun. 2003, pp. 61-62 http://ieeexplore.ieee.org/xpl/freeabs—all.jsp?arnumber=1221086.
T. Park, et al.; “Fabrication of Body-Tied FinFETs (Oega MOSFETs) Using Bulk Si Wafers”; 2003 Symposium on VLSI Technology Digest of Technical Papers; Jun. 2003, 2 pages.
U.S. Appl. No. 12/033,769, filed Feb. 19, 2008, Werner Juengling.
U.S. Appl. No. 12/033,780, filed Feb. 19, 2008, Werner Juengling.
U.S. Appl. No. 12/033,799, filed Feb. 19, 2008, Werner Juengling.
U.S. Appl. No. 12/052,300, filed Mar. 20, 2008, Werner Juengling.
U.S. Appl. No. 12/052,317, filed Mar. 20, 2008, Werner Juengling.
U.S. Appl. No. 12/052,537, filed Mar. 20, 2008, Werner Juengling.
U.S. Appl. No. 12/062,354, filed Apr. 3, 2008, Werner Juengling.
U.S. Appl. No. 12/130,825, filed May 30, 2008, Werner Juengling.
J-H. Ahn, S-H. Hong, S-J. Kim, J-B. Ko, S-W. Shin, S-D. Lee, Y-W. Kim, K-S. Lee, S-K. Lee, S-E. Jang, J-H. Choi, S-Y. Kim, G-H. Baw, S-W. Park, Y-J. Park, “An Experimental 256Mb Non-Volatile DRAM with Cell Plate Boosted Programming Technique”. IEEE International Solid-State Circuits Conference, ISSCC 2004 / Session 2 / Non-Volatile Memory / 2.2, 2004.
Bor-Wen Chan, Min-Hwa Chi, Liou, Y.H; Notch Elimination in Polycide Gate Stack Etching for Advanced DRAM Technology; Center for Technol. Dev., Worldwide Semicond. Manuf. Corp., Hsinchu; http://ieeexplore.ieee.org/xpl/freeabs—all.jsp?tp=&arnumber=883094&isnumber=19090.
Chien Yu, Rich Wise, Anthony Domenicucci; A Two-Step Spacer Etch for High-Aspect-Ration Gate Stack Process; IBM Microelectronics; http://www.mrs.org/s—mrs/s—mrs/sec—subscribe.asp?CID=2353&DID=113693&ation=detail.
Ikeda, H., Inukai, H.; High-Speed DRAM Architecture Development; NEC Corp., Sagamihara; Solid-State Circuits, IEEE Journal; May 1999; vol. 34, Issue 5, pp. 685-692; http://ieeexplore.ieee.org/xpls/abs—all.jsp?arnumber=760380&isnumber=16453.
Endoh, T., Shinmei, K., Sakuraba, H., Masuoka, F.; New Three-Dimensional Memory Array Architecture for Future Ultrahigh-Density DRAM; Res. Inst. Of Electrical Communication, Tohoku University, Sendai; Solid-State Circuites, IEEE Journal; Apr. 1999; vol. 34, Issue 4, pp. 476-483; hottp://ieeexplore.ieee.org/xpls/abs—all.jsp?arnumber=753680.
Takashima, D., Nakano, H.; A Cell Tra
Hall Jessica
Landau Matthew C
Micro)n Technology, Inc.
Yoder Fletcher
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