Electronic digital logic circuitry – Threshold – With field-effect transistor
Patent
1997-07-25
1999-08-24
Tokar, Michael
Electronic digital logic circuitry
Threshold
With field-effect transistor
326 35, 326 11, 326119, 327543, H03K 1923
Patent
active
059429127
ABSTRACT:
A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.
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IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992, Tadashi Shibata et al, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, pp. 1444-1455.
Luck Andreas
Schmitt-Landsiedel Doris
Thewes Roland
Weber Werner
Cho James H.
Siemens Aktiengesellschaft
Tokar Michael
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