Devices for non-volatile memory, systems and methods

Details Devices for non-volatile memory, systems and methods Devices for non-volatile memory, systems and methods

1992-10-13

1994-10-11

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257319, 365185, H01L 2978, H01L 2944, G11C 1134

Patent

active

053550072

ABSTRACT:
An electrically-erasable, electrically-programmable read-only memory cell is formed in a layer of semiconductor (1062) of a first conductivity type. A first heavily doped region (1022) and a second heavily doped region (1024) are formed in semiconductor layer (1062) to be of a second conductivity type opposite the first conductivity type. First heavily doped region (1022) is spaced from second heavily doped region (1024) by a first channel (1026). A gate conductor (1028) insulatively overlies channel (1026) for selectively controlling the conductance thereof. A third heavily doped region (1036) is formed in semiconductor layer (1062) to be of the second conductivity type. Third heavily doped region (1036) is separated from second heavily doped region (1024) by a channel (1038) and tunneling window (1040). A thin oxide tunneling window (1040) is formed overlying a portion of lightly doped region (1072) in channel (1038). A fourth heavily doped region (1042) is formed in the face of semiconductor layer (1062) to be of the second conductivity type. Fourth heavily doped region (1042) is spaced from third heavily doped region (1036) by a channel (1043). A lightly doped region (1049) is formed in semiconductor layer (1062) to be of the second conductivity type. A floating gate conductor (1020) is formed adjacent thin oxide tunneling window (1040), insulatively adjacent third channel (1043), insulatively adjacent channel (1038), and insulatively adjacent lightly doped region (1049).

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