Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2001-09-18
2003-03-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S039000, C326S040000, C708S625000, C708S650000, C708S505000
Reexamination Certificate
active
06538470
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic integrated circuit devices, and more particularly to programmable logic integrated circuit devices with integrated digital signal processing circuitry.
Programmable logic devices (“PLDs”) are well known as is shown, for example, by Jefferson et al. U.S. Pat. No. 6,215,326 and Ngai et al. U.S. Pat. No. 6,407,576. PLDs typically include many regions of programmable logic that are interconnectable in any of many different ways by programmable interconnection resources. Each logic region is programmable to perform any of several logic functions on input signals applied to that region from the interconnection resources. As a result of the logic function(s) it performs, each logic region produces one or more output signals that are applied to the interconnection resources.
The interconnection resources typically include drivers, interconnection conductors, and programmable switches for selectively making connections between various interconnection conductors. The interconnection resources can generally be used to connect any logic region output to any logic region input; although to avoid having to devote a disproportionately large fraction of the device to interconnection resources, it is usually the case that only a subset of all possible interconnections can be made in any given programmed configuration of the PLD.
One of the complexities that is faced in providing programmable logic devices involves the logic capacity of programmable logic devices. The demand for interconnection resources typically increases exponentially with respect to linear increases in logic capacity. Accordingly, interconnection arrangements that are flexible, efficient, and have sufficient signal carrying capacity are needed for programmable logic devices without displacing excessive amounts of other resources such as logic or without occupying a disproportionately larger area in PLDs.
Although only logic regions are mentioned above, it should also be noted that many PLDs also now include regions of memory that can be used as random access memory (“RAM”), read-only memory (“ROM”), content addressable memory (“CAM”), product term (“p-term”) logic, etc.
As the capacity and speed of PLDs has increased, interest in using PLDs for signal or data processing tasks (e.g., for digital signal processing tasks) that may involve relatively large amounts of parallel information and may require relatively complex manipulation, combination, and recombination of that information has increased. Large numbers of signals in parallel consume a correspondingly large amount of interconnection resources; and each time that information (or another combination or recombination that includes that information) must be routed within the device, another similar large amount of the interconnection resources is consumed. Some such PLDs may be programmable to perform signal and data processing tasks that involve relatively complex manipulation, combination, and recombination of information. However, such PLDs are often deficient in providing sufficient speed of operation, sufficient logic or interconnection resources to perform additional tasks, sufficient dedicated digital signal processing circuitry and interconnection resources (e.g., multistage digital signal processing circuitry), or in providing adequate implementation of common digital signal processing tasks without impairing the operation of a substantial portion of the PLD or occupying a substantial area in the PLD.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, programmable logic integrated circuit devices, methods, and systems may be provided that use or include digital signal processing regions. A programmable logic device may include a plurality of programmable logic regions and one or more digital signal processing regions. The regions may be arranged in different areas in the programmable logic device.
The programmable logic device may include programmable logic super-regions that may include groups of programmable logic elements, a memory region, and a digital signal processing region (e.g., a digital signal processing block). Different resources in a programmable logic device may be arranged in blocks. Each block may have a concentration of circuitry that is arranged to provide memory, programmable logic, or digital signal processing. The programmable logic device may include circuitry such as conductors and connectors for providing interconnect resources.
When a digital signal processing region is positioned in a programmable logic super-region, the digital signal processing region may use some of the local interconnect resources of the programmable logic elements, registers, and/or memory in that programmable logic super-region. Global interconnect resources of the programmable logic super-region may be used to apply input signals to the digital signal processing region and/or to route output signals out of the digital signal processing super-region.
A programmable logic device may include a column of programmable logic regions and may include a digital signal processing region in a row in that column. If desired, a programmable logic device may include a column of programmable logic regions and may include multiple rows in the column that include digital signal processing regions (e.g., each include a digital signal processing region). If desired, a programmable logic device may include a column of programmable logic regions and may include a digital signal processing region in a cell in a row in that column. The digital signal processing region may use local and global interconnect resources of an adjacent programmable logic region in the column. Such an arrangement may be used, when the digital signal processing region is approximately the same size as a programmable logic region. In some embodiments, a digital signal processing region substantially consumes the interconnect resources of an adjacent programmable logic region when the digital signal processing region is being used.
A digital signal processing region of a programmable logic device may perform multistage digital signal processing operations. A digital signal processing region of a programmable logic device may include a plurality of digital signal processing stages that are configurable to implement commonly used digital signal processing operations (e.g., commonly used filters). Multiplier circuits may be included in the digital signal processing region. Additional stages of the digital signal processing region may include stages that complement the functionality provided by the multiplier circuits. Circuitry in the additional stages may be interconnected with the multiplier circuits to implement commonly used digital signal processing operations. Additional stages may include circuitry that provides a multiply-and-add operation, a multiply-and-accumulate operation, or a multiply-and-subtract operation when used with the multiplier circuits.
The additional stages may include a stage that receives inputs from the multiplier circuits and applies an addition, a subtraction, or an accumulation operation to the received inputs. This stage may include circuits that are arranged (e.g., arranged to be dedicated) to perform addition, subtraction, and/or accumulation operations. The inputs of this stage may be dedicated to receiving outputs from the multiplier circuits. Local interconnect resources may be provided that include circuitry that is dedicated to routing the output signals of the multiplier circuits to the next stage of the digital signal processing region. Input register circuits may be included for feeding input signals to the multiplier circuits.
A next stage of the digital signal processing region may include an adder circuit. The adder circuit may perform an addition operation. The adder circuit may receive inputs from the previous stage, which may be the stage that applies an addition, a subtraction, or an accumulation operation to the outputs of the multiplier circuit stage mention
Hwang Chiao Kai
Langhammer Martin
Starr Gregory
Altera Corporation
Fish & Neave
Jackson Robert R.
Tan Vibol
Tokar Michael
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