Device with polymer layers and two-step self-aligned source...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S774000, C257S775000

Reexamination Certificate

active

07919810

ABSTRACT:
System and method for self-aligned etching. According to an embodiment, the present invention provides a method for performing self-aligned source etching process. The method includes a step for providing a substrate material. The method also includes a step for forming a layer of etchable oxide material overlying at least a portion of the substrate material. The layer of etchable oxide material can characterized by a first thickness. The layer of etchable oxide material includes a first portion, a second portion, and a third portion. The second portion is positioned between the first portion and the third portion. The method additionally includes a step for forming a plurality of structures overlying the layer of etchable oxide material. The plurality of structures includes a first structure and a second structure.

REFERENCES:
patent: 6025255 (2000-02-01), Chen et al.
patent: 6531359 (2003-03-01), Tempel et al.
patent: 6784056 (2004-08-01), Schneider et al.
patent: 7645667 (2010-01-01), Hong et al.
patent: 2006/0160308 (2006-07-01), Kim
Notice of Allowance for U.S. Appl. No. 11/611,363, mailed on May 15, 2009, 7 pages.
“Post Etch Residue(Polymer Removal),” Surface Preparation, Cleaning Post-Etch Residue (Polymer Removal); Applications Solutions Provider; Semitool Inc.; Jun. 26, 2006; 2 pages total. http://snf-www.stanford.edu/Process/PlasmaEtch/Oxide.html.
“Plasma Etch: Oxide Etch Overview,” Oxide Plasma Etching; Stanford Nanofabrication Facility; Jan. 21, 2009, 6 pages total. http://www.semitool.com/Post—Etch.html.
Requirement for Restriction/Election for U.S. Appl. No. 11/611,363 mailed on Mar. 26, 2009, 6 pages.

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