Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1998-06-08
2001-01-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S423000, C438S432000
Reexamination Certificate
active
06171927
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuit (“IC”) devices, and more particularly to non-uniform local oxidation to achieve differential field oxide thicknesses.
Local oxidation of silicon (“LOCOS”) is one type of method used to laterally isolate one device on an integrated circuit substrate from another device on the integrated circuit substrate. In a conventional LOCOS process, a layer of patterned silicon nitride is used as a mask in a thermal oxidation process. Even a thin layer of silicon nitride will prevent significant oxidation from occurring beneath it. The patterned silicon nitride layer allows field oxide to grow in the “window” regions while inhibiting oxide growth in the regions covered by silicon nitride. Unfortunately, oxide growth may occur underneath the edge regions of the silicon nitride layer to form what is commonly known as a “bird's beak”.
While silicon nitride is effective in preventing oxygen from diffusing through it to the underlying silicon substrate, and hence preventing the formation of an oxide layer, oxygen can still diffuse along the interface between the silicon nitride and the substrate. In some instances, a layer of pad oxide underlies the silicon nitride to reduce stress-related defects in the IC, and this pad layer can also act as a conduit for oxygen. In either instance, a bird's beak may form underneath the silicon nitride layer.
A desirable characteristic of the LOCOS process is that, after the field oxide is formed, the patterned silicon nitride layer can be stripped from the substrate to form what will become active cells between the regions of field oxide. These active cells are self-aligned to the field oxide, thus making efficient use of the valuable substrate area. Unfortunately, a bird's beak intrudes into the active cell region, reducing the area available for active device fabrication. As device geometries continue to shrink, the relative portion of the active cell area consumed by a bird's beak increases, decreasing the ultimate device density of the IC.
Multi-voltage ICs have an additional problem relating to the formation of bird's beaks. Many devices, such as dynamic random-access memories (“DRAMs”) and flash electronically erasable, programmable read-only memories (“flash EEPROMs”) use more than one voltage during operation. A low voltage may be used for one type of operation, such as a read/write or sense operation, while a higher voltage is used for a word-line boost operation or a floating-gate program/erase operation. ICs with integrated functions, such as memory and data processing functions, may also operate a more than one voltage. It is generally desirable to minimize the cell size, also known as the design rule, to decrease the IC size and hence cost for a given circuit. However, the ability of field oxide to isolate a voltage is generally related to the thickness of the field oxide. Unfortunately, the size of a bird's beak is generally related to the thickness of the field oxide that is grown. Therefore, field oxide that is thick enough to withstand the higher voltage results in an undesirably large bird's beak intruding into the active cell area of the lower voltage devices. Conversely, a field oxide optimized for the design rule of low-voltage cells might not reliably isolate high-voltage cells.
Therefore a multi-voltage IC with field oxidation that reliably isolates high voltages while allowing tighter design rules for low-voltage cells is desirable.
SUMMARY OF THE INVENTION
The present invention provides devices with differential filed oxide thicknesses and methods for making such devices. In one embodiment, a layer of silicon oxide is formed on a surface of a silicon substrate. A silicon nitride layer is formed over the layer of silicon oxide, and the silicon nitride layer is patterned to expose selected regions of the layer of silicon oxide. Selected regions of the exposed silicon oxide are covered with a mask, and the remaining exposed regions of the silicon oxide layer are nitridized by implanting nitrogen into the silicon oxide layer and/or silicon substrate. The mask is stripped and field oxide is grown in the exposed regions of the silicon oxide layer. During the field oxide growth process, the nitridized regions form silicon oxy-nitride, which inhibits oxide growth compared to the non-nitrided regions. After the field oxidation process, the field oxide is thicker in the non-nitrided regions than in the nitrided regions. In a particular embodiment, the non-nitrided field oxide regions are used to isolate an active cell containing a high-voltage memory device of a flash EEPROM memory cell from an active cell containing a low-voltage select transistor, and to isolate high-voltage active cells from each other and from low-voltage cells. The nitrided field oxide is used to isolate active cells containing low-voltage devices from each other. The high voltage is between about 8-9 V, and the low voltage is between about 3-5 V. In another embodiment, the exposed regions of the silicon oxide layer are nitrided by applying a substance that acts as a nitrogen source, such as dilute aqueous ammonia, to the exposed regions.
In another embodiment, the silicon nitride layer is patterned to expose a first set of regions of the silicon oxide layer. The first set of regions are nitrided by thermally treating the layer of silicon oxide in a nitrogen rich environment, such as an environment including ammonia. The silicon nitride layer is then patterned again to expose a second set of regions of the silicon oxide layer. Field oxide is grown in both the nitrided and non-nitrided exposed regions of the silicon oxide layer, the field oxide being thinner in the former than in the latter. In another embodiment, there is no layer of silicon oxide in the windows of the silicon nitride layer and the surface of the silicon substrate is nitrided.
These and other embodiments of the present invention, as well as some of its advantages and features are described in more detail in conjunction with the text below and attached figures.
REFERENCES:
patent: 5308787 (1994-05-01), Hong et al.
patent: 5358894 (1994-10-01), Fazan et al.
Chu Yuru
Sung Kuo-Tung
Lindsay Jr. Walter L.
Niebling John F.
Townsend and Townsend / and Crew LLP
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