Device, system and method of reduced-power memory address...

Details Device, system and method of reduced-power memory address... Device, system and method of reduced-power memory address...

2006-06-22

2009-12-15

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S001000, C711S002000, C711S200000, C711S203000, C711S213000

Reexamination Certificate

active

07634636

ABSTRACT:
Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.

REFERENCES:
patent: 5696507 (1997-12-01), Nam
patent: 6807616 (2004-10-01), McGrath et al.
patent: 6922769 (2005-07-01), Liron et al.
patent: 7103751 (2006-09-01), Toll et al.
patent: 2005/0216697 (2005-09-01), Liron et al.

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