Device, system and method for VLSI design analysis

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07073141

ABSTRACT:
A device, system and method for analysis of Very Large Scale Integration circuit designs. A computing platform may, for example, find one or more loops in a circuit design, functionally analyze the loops, and extract one or more Register-Transfer-level logical elements in relation to the analysis result. A computing platform may, for example, identify a group of at least one Channel Connected Sub-Network that forms at least one combinational loop, generate overall zero-delay collapsed functionality on an output of said group, identify one or more functional parts that form said group, and replace the group with one or more corresponding logically equivalent Register-Transfer-level devices.

REFERENCES:
patent: 6438734 (2002-08-01), Lu
patent: 6711534 (2004-03-01), Parashkevov
patent: 6745160 (2004-06-01), Ashar et al.
Novakovsky, S.; Shyman, S.; Hanna, Z.; “High capacity and automatic functional extraction tool for industrial VLSI circuit designs”; Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on Nov. 10-14, 2002 pp.: 520-525.
Jolly, Simon; Parashkevov, Atanas; McDougall, Tim: “Automated Equivalence Checking of Switch Level Circuits”, pp. 299-304; DAC 2002, Jun. 10-14, 2002, New Orleans, Louisiana, USA.
Kuehlmann, A.: Srinivasan, A.: “Verity—a formal verification program for custom CMOS circuits”: IBM Journal of Research & Development, Jan.-Mar. 1995, vol. 39, Issue 1 of 2, p. 149, 17p., 3 charts, 9 diagrams.
Fischer et al. “Abstraction of Schematic to High Level HDL. Design”, Technology, Intel Israel (74) Ltd. ICCAD 1990, pp. 90-96.
Kam et al., “Comparing Layouts with HDL Models: A Formal Verification Technique”, IEEE, 1992, pp. 588-591.
Kam et al., “State Machine Abstraction from Circuit Layouts using BDD's: Application in Verifications and Synthesis”, IEEE, 1992, pp. 92-97.
Lester et al.: LIP6/ASIM Laboratory, University Pierre et Marie Curie-Paris: “Yagle, a second generation functional abstractor for CMOS VLSI Circuits”, 1998, pp. 265-268.
Bryant:“Boolean analysis of MOS circuits”, IEEE Transaction on computer-aided design, vol. CAD-6, No. 4 Jul., 1987, pp. 634-649.
Bryant, “Extraction of gate level models from transistor circuits by four valued symbolic analysis”, IEEE, 1991, pp. 350-353.

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