Device structure for storing charge and method therefore

Details Device structure for storing charge and method therefore Device structure for storing charge and method therefore

2000-12-19

2002-09-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Fluid growth from gaseous state combined with preceding...

C438S257000

Reexamination Certificate

active

06444545

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to semiconductor devices and more particularly to a semiconductor storage device and a process for forming such a semiconductor storage device.
RELATED ART
Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile data storage. As is known, EEPROM device structures commonly include a floating gate that has charge storage capabilities. Charge can be forced into the floating gate structure or removed from the floating gate structure using control voltages. The conductivity of the channel underlying the floating gate is significantly altered by the presence of charges stored in the floating gate. The difference in conductivity due to a charged or uncharged floating gate can be current sensed, thus allowing binary memory states to be determined. The conductivity difference is also represented by a shift in the threshold voltage (Vt) associated with the device in the two different states.
As semiconductor devices continue to evolve, the operating voltages of such semiconductor devices are often reduced in order to suit low power applications. It is desirable for such operating voltage reductions to be accomplished while ensuring that the speed and functionality of the devices is maintained or improved.
One EEPROM device, which operates at lower operating voltages than a continuous floating gate device, uses a silicon-oxide-nitride-oxide-silicon (SONOS) structure, in which charge is stored in the nitride layer. Another advantage of SONOS over the continuous floating gate device is the ease of processing due to its simpler layer structure. In a SONOS structure, charge is forced from the substrate through the tunnel oxide into the nitride, which acts as a trapping layer. The trapping layer in SONOS is equivalent to the floating gate of other EEPROM devices. One problem that exists with the SONOS structure is that at temperatures greater than or equal to room temperature, the charge retention of the trapping layer can be a problem. The energy levels of the nitride traps are not deep enough to prevent, over the expected lifetime of the device, charge from thermally exciting into the nitride conduction band, then tunneling to the substrate layer through the first oxide (tunnel oxide). Hence, the charge retention and reliability of this structure is diminished. Therefore a need exists for a SONOS structure with a higher reliability, especially at temperatures equal to or greater than room temperature.


REFERENCES:
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Ilgweon Kim et al, “Room Temperature Single Electron Effects in a Si Nano-Crystal Memory”, Dec. 1999 IEEE Electron Device Letters, vol. 20, No. 12, pp. 630-631.
Ilgweon Kim et al., “Room Temperature Single Electron Effects in Si Quantum Dot Memory with Oxide-Nitride Tunneling Dielectrics”, 1988 IEEE, 4 pages.
Yang (Larry) Yang et al., “Reliability considerations in scaled SONOS nonvolatile memory devices”, Solid-State Electronics 43 (1999), pp. 2025-2032.

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