Device proxy agent for hiding computing devices on a...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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Details

C710S100000

Reexamination Certificate

active

06212587

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to configuring of computing devices on a computer bus, and more particularly, but not by way of limitation, to a method and apparatus for hiding computing devices connected to a Peripheral Component Interface bus from a host Central Processing Unit connected to the Peripheral Component Interface bus.
BACKGROUND OF THE INVENTION
Computer systems have achieved wide usage in modern society. During operation, a computer system processes and stores data at a speed and at a level of accuracy many times that which can be performed manually. Successive generations of computer systems have permitted ever-increasing amounts of data to be processed at ever-increasing rates.
Computer systems are sometimes operated as stand-alone devices or connected together by way of network connections, typically together with a network server, to form a computer network. When networked together, communication between the separate computer systems is possible. Files and other data, stored or generated at one computer system, can be transferred to another computer system.
A conventional computer system typically includes one or more Central Processing Units (CPUs) capable of executing algorithms forming applications and a computer main memory. Peripheral devices, both those embedded together with a CPU or constructed to be separate therefrom, also typically form portions of a conventional computer system. Computer peripheral devices include, for instance, video graphics adapters, Local Area Network (LAN) interfaces, Small Computer System Interface (SCSI) bus adapters, and mass storage devices, such as disk drive assemblies.
A computer system further typically includes computer buses which permit the communication of data between various portions of the computer system. For example, a host bus, a memory bus, at least one high-speed bus, a local peripheral expansion bus, and one or more additional peripheral buses form portions of a typical computer system.
A peripheral bus is formed, for instance, of an SCSI bus, an Extension to Industry Standard Architecture (EISA) bus, an Industry Standard Architecture (ISA) bus, or a Peripheral Component Interface (PCI) bus. The peripheral bus forms a communication path to and from a peripheral device connected thereto. The computer system CPU, or a plurality of CPUs in a multi-processor system, communicates with a computer peripheral device by way of a computer bus, such as one or more of the computer buses noted above.
Data is communicated to and from a computer peripheral device by way of a computer bus. A computer peripheral, depending upon its data transfer speed requirements, is connected to an appropriate computer bus, typically by way of a bus bridge that detects required actions, arbitrates, and translates both data and addresses between the various buses.
A computer peripheral device forming a portion of a single computer system might well be supplied by a manufacturer other than the manufacturer of the computer CPU. If the computer system contains more than one peripheral device, the peripheral devices might also be supplied by different manufacturers. Furthermore, the computer system may be operable pursuant to any of several different operating systems. The various combinations of computer peripheral devices and computer operating systems of which a computer system might be formed quickly becomes quite large.
Software drivers are typically required for each computer peripheral device to effectuate its operation. A software driver must be specifically tailored to operate in conjunction with the particular operating system operating on the computer. A multiplicity of software drivers might have to be created for a single computer peripheral to ensure that a computer peripheral device is operable together with any of the different operating systems.
The complexity resulting from such a requirement has led, at least in part, to the development of an Intelligent Input/Output (I
2
O) standard specification. The I
2
O standard specification sets forth, inter alia, standards for an I/O device driver architecture that is independent of both the specific peripheral device being controlled and the operating system of the computer system to which the device driver is to be installed.
In the I
2
O standard specification, the portion of the driver that is responsible for managing the peripheral device is logically separated from the specific implementation details of the operating system with which is to be installed. By doing so, the part of the driver that manages the peripheral device becomes portable across different computer and operating systems. The I
2
O standard specification also generalizes the nature of communication between the host computer system and peripheral hardware, thus, providing processor and bus technology independence.
In order to incorporate I
2
O technology in a computer system and realize the benefits afforded by the I
2
O technology, operating systems need to differentiate between peripheral devices which are under the control of an I
2
O Input / Output Processor (IOP) and peripheral devices which are not. Although system software which is I
2
O compliant is capable of making this distinction, legacy software, that is, software developed and deployed prior to the I
2
O standard or which is otherwise not I
2
O compliant, cannot. Therefore, to retain the investment made in the legacy software through its continued use while at the same time realizing the benefits of the I
2
O technology, an alternate approach is needed to make the distinction. The current method used to address this problem involves the use of a PCI-to-PCI bridge and an i960 private address space mechanism both of which are well known in the industry. Devices under the control of an I
2
O IOP are “hidden” from the host CPUs and their related software by placing these devices behind a PCI-to-PCI bridge and allocating memory space to the PCI bus behind the bridge for storing information pertaining to these devices. The address space allocated to the PCI bus behind the bridge is inaccessible by the host CPUs and, thus, the host CPUs do not know of the existence of these devices and cannot directly access them. All access to these devices is effectuated via the I
2
O IOP.
A limitation of the current approach of hiding devices under the control of an I
2
O IOP is that they need to be placed behind the bridge thereby requiring a PCI-to-PCI bridge and its associated hardware and software which adds additional cost to the computer system. It would be advantageous, therefore, to devise a method and apparatus capable of hiding peripheral computing devices located in front of the bridge from host CPUs. Such a method and apparatus would prevent host CPUs from attempting to access the devices which are under the control of the I
2
O IOP.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for hiding computing devices on a computer bus comprising a computer memory for storing information pertaining to computing devices, a device proxy agent for reserving memory for storing information pertaining to hidden devices and an IOP, which in conjunction with the device proxy agent, assigns the memory space assigned to the device proxy agent to hidden devices. A section of memory is allocated as memory address space for the computer bus. A first portion of the allocated memory address space is assigned to non-hidden computing devices and a second portion of the allocated memory address space is assigned to the device proxy agent. The IOP in conjunction with the device proxy agent assigns the memory address space assigned to the device proxy agent to the hidden devices.


REFERENCES:
patent: 5548730 (1996-08-01), Young et al.
patent: 5734847 (1998-03-01), Garbus et al.
Mendel, Brett; “Server I/O all set to flow”;Lantimes, Oct. 27, 1997, vol. 14, Issue 22; cover page and p. 31.
Briggs, Chris; “Smarter and Faster I/O for Servers”; CORE: Operating Systems;Byte, May 1, 1996, vol. 2, No. 5.
Thompson, Tom; “I2O Bea

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