Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-10-04
2001-06-05
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S754090, C324S762010, C324S765010, C439S331000, C029S840000, C029S593000, C430S317000
Reexamination Certificate
active
06242933
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and, more particularly, to a method and apparatus for final testing semiconductor devices, such as of Ball Grid Array (BGA), Chip Scale Packaging (CSP), Quad Flat Pack (QFP), Quad Flat No-Lead (QFN) Integrated Circuit chips and others, that are mounted on strips.
(2) Description of the Prior Art
A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mils. spacings in regular and staggered array patterns.
In order to test a BGA device, the contactor elements of the BGA device are inserted into a contactor plate having a plurality of sockets. The contactor plate is coupled to a Device Under Test (DUT) loadboard, which is coupled to a testing machine. The DUT loadboard is in essence a printed circuit board that completes electrical connections between the BGA contactor elements via the contactor plate and the tester. In order to test the BGA device, the tester sends signals to and receives signals from the BGA device via the electrical conductor paths provided by the contactor plate and the DUT board.
At present the final testing of semiconductor Integrated Circuits is performed using Integrated Circuit Handler apparatus whereby each of the IC packages is handled as an individual unit and is advanced to the test socket of the DUT by either gravity feed or by using pick and place methods.
Mass production of semiconductor Integrated Circuits (IC's) brings with it the requirement that these IC's can be tested at high speed. Current trends in the semiconductor industry also promote convenient and bulk handling of semiconductor chips. While high speed testing has been current practice in the industry for a number of years, this testing in most cases handles individual chips. By mounting individual chips onto strips the flow of chips through the manufacturing and testing cycles can be greatly facilitated. This improved capability of handling a larger number of chips has to be accompanied with corresponding improvements in the testing capabilities for these chips. Moreover, strip testing also eliminates the use of trays for transportation and storage of individual chips throughout the whole testing process. This results in requirements for improved capabilities of handling chips that are mounted on strips in a testing environment. These improved capabilities transport chips at a rapid rate in and out of the test position. While in the test position, the chips must be contacted in a rapid and dependable way so that the chip can be tested. This contacting of the chip while the chip is in the position where it can be tested is done by means of probe sockets. The invention addresses a probe socket design that meets the requirements of rapidly and dependably contacting semiconductor devices for the purpose of testing these devices.
The present invention teaches an apparatus and method for testing integrated semiconductor circuits by means of device or package strip testing using probing techniques with a probe socket.
U.S. Pat. No. 5,355,079 (Evans et al.) shows a probe assembly for testing IC devices.
U.S. 5,420,506 (Lin) teaches an apparatus and method for testing packages.
U.S. Pat. No. 5,843,808 (Karnezos) shows a TAB grid array package made in strips.
U.S. Pat. No. 5,852,870 (Freyman et al.) teaches a Grid array assembly that includes a test step.
U.S. Pat. No. 4,816,754 (Buechele et al.) and U.S. Pat. No. 5,419,710(Pfaff) and U.S. Pat. No. 5,656,942(Watts) show various tester and holders. However, these references differ from the exact process of the invention.
SUMMARY OF THE INVENTION
It is the objective of the invention to provide apparatus and method for testing integrated semiconductor circuits by means of device strip testing using probing techniques with a probe socket.
The invention teaches, in accordance with the objective of the invention, a new probe socket that allows for high speed and dependable contacting of points of contact on the Device Under Test. The new probe socket is aimed at a testing environment where semiconductor devices are mounted on device or package strips.
REFERENCES:
patent: 4816754 (1989-03-01), Buechele et al.
patent: 5180974 (1993-01-01), Mitchell et al.
patent: 5355079 (1994-10-01), Evans et al.
patent: 5410258 (1995-04-01), Bowers et al.
patent: 5419710 (1995-05-01), Pfaff
patent: 5420506 (1995-05-01), Lin
patent: 5517125 (1996-05-01), Posedel et al.
patent: 5656942 (1997-08-01), Watts et al.
patent: 5694049 (1997-12-01), Singh et al.
patent: 5742170 (1998-04-01), Issac et al.
patent: 5843808 (1998-12-01), Karnezos
patent: 5852870 (1998-12-01), Freyman et al.
patent: 5859538 (1999-01-01), Self
patent: 5869976 (1999-02-01), Kelley et al.
patent: 5896037 (1999-04-01), Kudla et al.
patent: 5990692 (1999-11-01), Jeong et al.
patent: 6060893 (2000-05-01), Farnworth et al.
patent: 6104201 (1998-06-01), Beaman et al.
Ackerman Stephan B.
Brown Glenn W.
Hamdan Wasseem H.
Saile George O.
ST Assembly Test Services
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