Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-20
2004-08-10
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
06775818
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of circuit simulators, and more particularly to a circuit simulator that utilizes optical proximity correction.
BACKGROUND OF THE INVENTION
Current circuit, gate, or device parameter simulation is derived through chip geometries and layouts generated by designers before any optical corrections (such as those required for optical proximity effects) are made to the layout. Circuit, gate, or device parameter simulations are conducted at the front end of the design cycle before any photolithographic parameters that will be used in manufacturing are known. In fact, the circuit, gate, or device parameter simulations use textbook equations and do not incorporate real life effects present in rigorously derived wafer level images. Instead, the existing approaches to front end design simulations use “rule of thumb” guard bands to account for process variations that occur during the manufacture of devices, such as scaling factors of +/−10% to account for any non-idealities generated during the process of pattern transfer on the wafer. While such approximations may have been sufficient when the circuit geometries were much larger, the errors introduced are substantial with shrinking features. In some cases, these simulations diverge significantly from electrically measured values downstream after manufacturing is complete. In other cases, Monte Carlo simulations attempt to statistically predict random process variations but have no way of including systematic process variations.
Thus, as described above, existing front-end design methods for predicting gate-level and device performance do not rigorously account for systematic process effects that occur during pattern transfer to a wafer, such as optical proximity due to varying pitches, pattern density loading, or plasma loading. These effects are taken into account in lithographic simulations, which are done completely separate from front end design simulations. However, such lithographic simulations are currently used only one mask at a time. One exemplary approach is to determine the behavior of the images on the wafer through changing process conditions, such as when the focus on the stepper shifts away from a preset position. Various optical effects that occur during the lithographic pattern transfer through the stepper lens onto the wafer are not considered. Thus, the current applications of lithographic simulations are exclusively limited to predicting image quality of individual layers on the wafer. The concept of extending this to multiple layers and “connecting” them to derive electrical characteristics does not exist.
Furthermore, current front end electronic design automation (EDA) tools lack the ability to incorporate such effects and, instead, rely upon gross approximations. As a result, the predicted electrical characteristics may differ from actual wafer level results substantially.
Therefore, it would be desirable to provide a comprehensive simulation of a circuit, gate, or device parameter by including processing information of the circuit on a substrate.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method and system for simulating a circuit, gate, or electrical device parameter utilizing the conditions of mask replicating onto wafer integrated circuit manufacture as part of the processing calculations.
The present invention provides a gate-specific, cell-specific or full chip transistor parametric map for designers before a mask is made. Different optical proximity correction models may be compared on this basis, such as cores, memory cells, analog blocks, and other functional modules that may violate electrical design rules for a given optical proximity correction model. Also, parasitic effects, one of the biggest drawbacks of current EDA tools, are considered. A rigorously obtained wafer level simulation (correlated and calibrated with wafer images) provides a powerful tool for static and dynamic parasitic extraction. Further, by selectively choosing the longest routing length between bottleneck logic/memory modules, worst-case delay can be calculated more accurately. This look ahead capability may also be used to make business related decisions, such as whether to use the full reticle (or mask) for a given chip or whether to restrict field size (i.e., the number of die per field) for logic modules.
The method of the present invention may also be used for fine tuning a circuit, gate, or device parameter simulation program, integrated circuit emphasis (SPICE) models, that currently takes a long time due to the need for wafer level data. The advantage of optical proximity correction code, such as the one described in U.S. Pat. No. 6,081,659, for scanning electron microscope (SEM) image calibration may be extended to use etched rather than resist images for a better prediction of the final electrical output, if needed.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5991477 (1999-11-01), Ishikawa et al.
patent: 6334209 (2001-12-01), Hashimoto et al.
patent: 2002/0166107 (2002-11-01), Capodieci et al.
Callan Neal
Strelkova Nadya
Taravade Kunal
Do Thuan
LSI Logic Corporation
Suiter - West PC LLO
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