Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-03
2003-03-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C702S118000, C703S014000, C326S047000, C326S102000, C257S356000, C324S754090, C700S109000
Reexamination Certificate
active
06530068
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to design and manufacture of semiconductors and, in particular, to transistor characterization and modeling structures.
BACKGROUND OF THE INVENTION
The design and development of semiconductors and integrated circuits is a complex and involved process requiring repeated testing and evaluation of circuit design and performance. Likewise, the fabrication of semiconductors and integrated circuits requires a high degree of precision in process control, equipment operation, and material manufacture. Throughout the design and fabrication process, various tests and measurements are made to determine the function of individual components, as well as to monitor the quality of the manufacturing process. As a consequence, transistor characterization and modeling structures are often included on the wafers along with the integrated circuits to perform many of these tests.
During the design and development stages of an integrated circuit, transistor modeling structures residing on development test chips or on Process Control Monitor test chips (PCM's) are commonly used for device modeling and transistor process characterization. For example, a particular integrated circuit may use numerous types of semiconductor devices or transistors. Each of these devices must be modeled and characterized separately to determine its functional properties and operating characteristics. Modeling of these devices is typically accomplished by fabricating a range of different device geometries (e.g., different gate lengths or source/drain channel widths) for each device on a modeling test structure. Each device geometry can then be subjected to electrical testing to determine its operational performance (i.e., transistor characterization). Analysis of the operational performance of each device geometry can then be used to develop a complete model of the operational characteristics of the device for a particular range of geometries.
One typical example of a conventional modeling structure for a MOSFET transistor (metal-oxide-silicon, field effect transistor) comprises a 46-pad test tile. One pad is used for a common gate, one pad is used for a common source, and one pad is used for a common P-substrate (for N-channel transistors). One pad is also used for a common N-well when modeling P-channel transistors (in an N-well in a P-substrate). Each of the remaining forty-two (42) pads is connected to a separate transistor drain. Accordingly, a conventional 46-pad test tile can only support forty-two (42) separate transistor geometries.
As integrated circuits become more complex, the number of devices and transistor types used in the circuit increases. The increased number of devices and transistor types require a corresponding increase in the number of modeling test structures. Similarly, as transistors become smaller and all more sophisticated, their operational characteristics become less predictable. It is therefore often necessary to test additional transistor geometries to develop an accurate and complete model of the transistor's operational characteristics. Additional test geometries also reduce the need for, and reliance on, interpolation calculations for non-tested geometries.
Modeling structures, however, are relatively large as compared to the size of the devices being tested. This is primarily the result of the test pads, which must be of sufficient size to enable contact with the testing probes. This results in certain limitations on the number of test structures that can be created or utilized on a given wafer, particularly if the wafer also contains product die. Moreover, the greater the amount of wafer space allocated to test structures, the less wafer space available for product die. There is consequently a need for a modeling structure that can incorporate and test a greater number of devices and/or device geometries.
Test structures are also required during semiconductor and integrated circuit production fabrication. Most test structures are located within the scribe lines between product die. Most of these test structures are used to monitor the process and basic device characteristics and functionality (i.e., to identify incorrectly processed material). These test structures are discarded once the product die are packaged. Scribe line monitors, for example, are destroyed when the wafer is separated into individual die.
The scribe line area between adjacent die is relatively small. Because of this constraint on wafer space, it is not unusual for a typical scribe line monitor to have very few test pads. Typical scribe line monitors are consequently very limited in their testing functions. Accordingly, there is also a need for an improved scribe line monitor that will overcome these limitations and provide a greater range of testing and device characterization functions.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a multiplexed transistor modeling structure that enables testing of a plurality of transistors. The modeling structure comprises a plurality of separate transistor groups, wherein each separate transistor group comprises a plurality of individual transistors. Each individual transistor comprises a source, a drain, a substrate, and a gate. A common source pad on the modeling structure is connected to the source of each of the individual transistors. A common substrate pad is likewise connected to the substrate of each of the individual transistors.
The modeling structure further comprises a plurality of drain pads, one drain pad for each separate transistor group. Each drain pad is connected to the drains of each of the individual transistors of one transistor group. The modeling structure also comprises a plurality of gate pads, one gate pad for each of the transistors in a transistor group. Each gate pad is connected to the gate of one individual transistor in each transistor group. Consequently, each individual transistor is connected to a different gate and drain pad combination, thereby permitting each transistor to be individually tested.
The preferred embodiment of the invention includes features in addition to those listed above. Moreover, the advantages over the current art discussed above are directly applicable to the preferred embodiment, but are not exclusive. The other features and advantages of the present invention will be further understood and appreciated when considered in relation to the detailed description of the preferred embodiment.
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Cao Huazhe
Qian Mimi Xuefeng
Rogers David Michael
Advanced Micro Devices , Inc.
Kik Phallaka
Siek Vuthe
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