Device, method, and integrated circuit for rectangular image...

Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer

Reexamination Certificate

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Details

C345S562000, C345S533000

Reexamination Certificate

active

07830393

ABSTRACT:
In the case where a previous character (P1) is cleared on a screen (20) and a new character (P2) is displayed on the right of the previous one, first, image data to be transferred (P2) is prepared in a source image memory. Next, a write start address (W) is set at the head of a bit sequence of a left clearance width (LC)×BPP, which precedes the destination address (T) of a frame buffer into which the head (S) of the image data (P2) is to be written. After that, a series of burst transfer repeatedly copies clearance data held in a register into a region of the left clearance width (LC), starting from the write start address (W), and subsequently writes one line (a transfer width (W1)×BPP) of the image data (P2). The write start address is incremented by a frame width (FW)×BPP.

REFERENCES:
patent: 5293596 (1994-03-01), Toyokura et al.
patent: 5644758 (1997-07-01), Patrick et al.
patent: 5717848 (1998-02-01), Watanabe et al.
patent: 6992648 (2006-01-01), Yamada
patent: 4-218847 (1992-08-01), None
patent: 2001-209370 (2001-08-01), None
patent: 2002-140702 (2002-05-01), None

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