Device manufacturing method and computer program product

Details Device manufacturing method and computer program product Device manufacturing method and computer program product

2011-03-01

2011-03-01

Olsen, Allan (Department: 1716)

Etching a substrate: processes

Masking of a substrate using material resistant to an etchant

C216S059000, C700S121000

Reexamination Certificate

active

07897058

ABSTRACT:
A method of forming features, e.g. contact holes, at a higher density than is possible with conventional lithographic techniques involves forming an array of sacrificial positive features, conformally depositing a sacrificial layer so that negative features are formed interleaved with the positive features, directionally etching the sacrificial layer and removing the sacrificial features. The result is an array of holes at a higher density than the original sacrificial features. These may then be transferred into the underlying substrate using a desired process. Also, the method may be repeated to create arrays at even higher densities.

REFERENCES:
patent: 4496216 (1985-01-01), Cowan
patent: 5328810 (1994-07-01), Lowrey et al.
patent: 5420067 (1995-05-01), Hsu
patent: 5618383 (1997-04-01), Randall
patent: 5759744 (1998-06-01), Brueck et al.
patent: 5795830 (1998-08-01), Cronin et al.
patent: 5856049 (1999-01-01), Lee
patent: 6042998 (2000-03-01), Brueck et al.
patent: 6063688 (2000-05-01), Doyle et al.
patent: 6204187 (2001-03-01), Rupp et al.
patent: 6337173 (2002-01-01), Jen et al.
patent: 6482731 (2002-11-01), Juengling
patent: 6589713 (2003-07-01), Okoroanyanwu
patent: 6636294 (2003-10-01), Kochi
patent: 6638441 (2003-10-01), Chang et al.
patent: 6936899 (2005-08-01), Juengling
patent: 7312158 (2007-12-01), Miyagawa et al.
patent: 7358140 (2008-04-01), Furukawa et al.
patent: 7476933 (2009-01-01), Juengling
patent: 7531456 (2009-05-01), Kwon et al.
patent: 2003/0203320 (2003-10-01), Sabnis et al.
Australian Examination Report issued on Oct. 29, 2008 in Singapore Application No. 200700939-2.
J.P. Long et al., “Edge Defined Lithography for Nano-scale III-N. Field Effect Transistors”, The International Conference on Compound Semiconductor Manufacturing Technology 2005 On-line Digest, available at http:///www.gaasmantech.org/Digests/2005/index.htm, No. 14.22.
Yang-Kyu Choi et al., “A Spacer Patterning Technology for Nanoscale CMOS”, IEEE Transactions on Electron Devices, vol. 49, No. 3 (Mar. 2002).
Zhaoning Yu et al., “Fabrication of Large Area 100 nm Pitch Grating by Spatial Frequency Doubling and Nanoimprint Lithography for Subwavelength Optical Applications”, J. Vac. Sci. Technology. B 19(6), Nov./Dec. 2001, pp. 2816-2819.
European Search Report issued for European Patent Application No. 07250479.8-1235, dated Sep. 18, 2007.

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