Device lithography using multi-level resist systems

Details Device lithography using multi-level resist systems Device lithography using multi-level resist systems

1984-05-21

1985-07-30

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156643, 156646, 1566591, 427 431, 430312, 430313, 430327, 430330, G03C 500, B44C 122, C03C 1500, B05D 306

Patent

active

045320055

ABSTRACT:
In order to hard-bake the bottom resist layer of a tri-level resist system for patterning a device wafer, the resist is subjected to a positive ramp heating step (of increasing ambient temperatures).

REFERENCES:
patent: 4244799 (1981-01-01), Fraser et al.
patent: 4343677 (1982-08-01), Kinsbron et al.
patent: 4426247 (1984-01-01), Tamamura et al.
patent: 4481049 (1984-11-01), Reichmanis et al.

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