Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-09-25
2000-08-08
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711150, 711151, 711152, 711158, 711163, G06F 1730
Patent
active
061015881
ABSTRACT:
A mass storage subsystem is used with a digital data processing system, the digital data processing system also including at least one host computer for generating access requests. The mass storage subsystem includes a data storage subsystem, a cache memory and a host adapter. The data storage subsystem includes at least one data storage device, the data storage device including a plurality of logical data store, each for storing a plurality of data items. Each data storage device is associated with a respective device lock used regulate access thereto. The cache memory includes a plurality of cache slots each caching data items from respective logical data stores. Each cache slot is associated with a slot lock for use in regulating access thereto. The host adapter receives access requests from the host computer, and is responsive to each access request to initially determine whether it holds the device lock associated with the data storage device containing the data item to be accessed in response to the respective access request. The host adapter, in response to a negative determination, determines whether the logical data store containing the data item to be accessed is said at least one cache slot and, if so, uses the slot lock associated therewith to control access thereby to the data item to be accessed.
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Cabeca John W.
EMC Corporation
Gunther John M.
Jordan Richard A.
Tzeng Fred F.
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